JPH07101741B2 - Method for manufacturing vertical MOSFET - Google Patents
Method for manufacturing vertical MOSFETInfo
- Publication number
- JPH07101741B2 JPH07101741B2 JP63235827A JP23582788A JPH07101741B2 JP H07101741 B2 JPH07101741 B2 JP H07101741B2 JP 63235827 A JP63235827 A JP 63235827A JP 23582788 A JP23582788 A JP 23582788A JP H07101741 B2 JPH07101741 B2 JP H07101741B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- diffusion layer
- forming
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000007772 electrode material Substances 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 238000001020 plasma etching Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Description
【発明の詳細な説明】 （イ） 産業上の利用分野 本発明は縦型のMOSFETに関し、主としてＰチャンネルMO
SFETを対象とする。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a vertical MOSFET, and is mainly a P-channel MO
Target SFET.
（ロ） 従来の技術 ＮチャンネルFETにコンプリメンタリー（相補的）に組
合せ、又は単独の素子として大電流のスイッチング動作
を行わせる目的で、しばしばＰチャンネル型の電力用FE
Tが必要とされている。かかる用途や目的のために電力
用の大電流・高耐圧のFETを得るには、その特性上、ド
レイン電極が基板となる縦型のFETが適合している。す
なわち第２図に示す如く、裏面にP+型層（１）を有する
Ｐ型半導体基体（２）の主表面に形成したＮ型拡散層
（３）の一部にP+型ソース領域（４）とその電極（５）
及びゲート電極（６）を設け、基体（２）の裏面からド
レイン電極（７）を取り出すことにより、単位面積当り
のFET動作する活性面積が大きくとれ、その結果ドレイ
ンソース間のオン抵抗の低減、相互コンダクタンスの増
大、したがって電流容量の増大といった目的が達せられ
る。(B) Conventional technology P-channel power FE is often used for complementary (complementary) combination with an N-channel FET or as a single element to perform high-current switching operation.
T is needed. In order to obtain a high current / high withstand voltage FET for electric power for such purposes and purposes, a vertical FET having a drain electrode as a substrate is suitable because of its characteristics. That is, as shown in FIG. 2, the P + type source region (4) is formed in a part of the N type diffusion layer (3) formed on the main surface of the P type semiconductor substrate ( 2 ) having the P + type layer (1) on the back surface. ) And its electrodes (5)
By providing the gate electrode (6) and taking out the drain electrode (7) from the back surface of the substrate ( 2 ), a large active area for FET operation per unit area can be obtained, and as a result, the on-resistance between the drain and source can be reduced. The goals of increasing transconductance and thus increasing current capacity can be achieved.
ところで、ソース電極（５）としては取扱いの容易さか
ら一般にアルミニウム（Al）又はアルミニウム・シリコ
ン（Al-Si）が用いられているが、アルミニウムはシリ
コン（Si）に対してＰ型不純物としての特性を有する
為、Ｎ型拡散層（３）とでPN接合によるバリア（障壁）
を形成し、これが素子の特性を劣化させる。By the way, aluminum (Al) or aluminum-silicon (Al-Si) is generally used as the source electrode (5) because it is easy to handle. However, aluminum is a p-type impurity with respect to silicon (Si). Since it has an N-type diffusion layer (3), it is a barrier due to a PN junction.
Are formed, which deteriorates the characteristics of the device.
この様な欠点に対し、同じく第２図に示すようにＮ型拡
散層（３）表面にN+型の高濃度コンタクト領域（８）を
形成することによりソース電極（５）とＮ型拡散層
（３）とのオーミック性を改善する技術が特開昭58-165
69号公報（H01L 29/78）に記載されている。Against such a drawback, the source electrode (5) and the N-type diffusion layer are formed by forming an N + -type high-concentration contact region (8) on the surface of the N-type diffusion layer (3) as shown in FIG. A technique for improving ohmic contact with (3) is disclosed in JP-A-58-165.
No. 69 (H01L 29/78).
（ハ） 発明が解決しようとする課題 しかしながら、P+型ソース領域（４）とソース電極
（５）とは電流容量を確保する為ある程度のコンタクト
面積を必要とすることから、ホトレジスト処理によりN+
型コンタクト拡散層（８）を選択的に形成することは素
子の微細化を押し進める上で弊害となる欠点を有してい
る。(C) Problems to be Solved by the Invention However, since a certain contact area is required between the P + type source region (4) and the source electrode (5) in order to secure the current capacity, N + is obtained by the photoresist treatment.
The selective formation of the type contact diffusion layer (8) has a drawback that it is a detrimental factor in promoting miniaturization of the device.
（ニ） 課題を解決するための手段 本発明は斯上した欠点に鑑み成されたもので、ゲート電
極（17）材料によってＮ型拡散層（20）表面に残存膜
（18）を残し、この残存膜（18）を利用してセルフアラ
イン的にN+型コンタクト拡散層（25）を形成することに
より、微細化に適した縦型MOSFETの製造方法を提供する
ものである。(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and leaves the residual film (18) on the surface of the N-type diffusion layer (20) by the material of the gate electrode (17), A method for manufacturing a vertical MOSFET suitable for miniaturization is provided by forming an N + -type contact diffusion layer (25) in a self-aligned manner using the residual film (18).
（ホ） 作用 本発明によれば、残存膜（25）によってP+型ソース領域
（21）とN+型コンタクト層（25）との双方がセルフアラ
インにより形成できるので、マスク合せ精度が不要とな
り微細化が可能になる。(E) Function According to the present invention, both the P + type source region (21) and the N + type contact layer (25) can be formed by self-alignment by the residual film (25), so that mask alignment accuracy is not required. Enables miniaturization.
（ヘ） 実施例 以下、本発明の一実施例を図面を参照しながら詳細に説
明する。本発明の目的はこのような縦型のＰチャンネル
電力用FETを提供することにある。本発明によるＰチャ
ンネルMOSFETは第１図（ａ）〜（ｋ）で示す各工程のプ
ロセスに従って製造される。(F) Example Hereinafter, one example of the present invention will be described in detail with reference to the drawings. An object of the present invention is to provide such a vertical P-channel power FET. The P-channel MOSFET according to the present invention is manufactured according to the process of each step shown in FIGS.
（ａ） まず、Ｂ（ボロン）を高濃度にドープしたP+型
Si基板（11）上に低濃度のＰ型エピタキシャル成長層
（12）を形成したP-P+型基体（13）を用意する。(A) First, P ( +) type heavily doped with B (boron)
A P − P + type substrate ( 13 ) having a low concentration P type epitaxial growth layer (12) formed on a Si substrate (11) is prepared.
（ｂ） この基体（13）表面にホトレジスト処理した酸
化膜（14）をマスクにして選択的にＮ型のＮ型拡散層
（15）を形成する。この部分は前記基板に対し部分的に
深く存在させる。(B) An N-type N-type diffusion layer (15) is selectively formed on the surface of the substrate ( 13 ) using the photoresist-processed oxide film (14) as a mask. This portion is partially deep with respect to the substrate.
（ｃ） しかる後、ゲートとなる部分に熱酸化により新
たにゲート酸化膜（16）を形成する。このときFETの周
囲のフィールド部には最初の厚い酸化膜（14）をそのま
ま残存させる。この後全面にポリシリコン層をデポジッ
トし、ホトレジスト処理によってポリシリコン層を選択
的にエッチング除去することによりゲート酸化膜（16）
上にはゲート電極（17）を、Ｎ型拡散層（15）上のゲー
ト酸化膜（16）上には本発明の構成に欠くことのできな
い残存膜（18）を形成する。(C) After that, a gate oxide film (16) is newly formed on the portion to be the gate by thermal oxidation. At this time, the first thick oxide film (14) is left as it is in the field portion around the FET. After that, a polysilicon layer is deposited on the entire surface, and the polysilicon layer is selectively etched and removed by a photoresist process to form a gate oxide film (16).
A gate electrode (17) is formed on the upper surface, and a residual film (18) which is indispensable for the structure of the present invention is formed on the gate oxide film (16) on the N-type diffusion layer (15).
（ｄ） 続いてゲート電極（16）と残存膜（18）をマス
クとし、チャンネル形成のためのＮ型領域（19）をイオ
ン注入又はデポジットと熱拡散により選択的に形成す
る。前記熱拡散によりＮ型領域（19）はゲート電極（1
7）の下部に横方向拡散により廻り込んでチャンネル部
を形成し、さらに先に形成した深いＮ型拡散層（15）と
連結して同図に示す形状のＮ型拡散層（20）を形成す
る。(D) Then, using the gate electrode (16) and the remaining film (18) as a mask, an N-type region (19) for forming a channel is selectively formed by ion implantation or deposit and thermal diffusion. Due to the thermal diffusion, the N-type region (19) becomes a gate electrode (1
A channel portion is formed by wrapping around in the lower part of 7) by lateral diffusion, and further connected to the deep N-type diffusion layer (15) formed earlier to form an N-type diffusion layer (20) of the shape shown in the figure. To do.
（ｅ） 次にゲート電極（17）と残存膜（18）を再びマ
スクとして、P+型ソース領域（21）をイオン注入又はデ
ポジットと熱処理によりＮ型拡散層（20）表面に選択的
に形成する。結果、P-型エピタキシャル層（12）とP+型
ソース領域（21）とに挟まれたＮ型拡散層（20）表面が
チャンネルとなる。本工程は残存膜（18）を利用するの
で、ホトレジスト工程は一切必要無い。(E) Next, using the gate electrode (17) and the remaining film (18) as a mask again, a P + type source region (21) is selectively formed on the surface of the N type diffusion layer (20) by ion implantation or deposit and heat treatment. To do. As a result, the surface of the N type diffusion layer (20) sandwiched between the P − type epitaxial layer (12) and the P + type source region (21) becomes a channel. Since the remaining film (18) is used in this step, no photoresist step is required.
（ｆ） その後ゲート電極（17）と残存膜（18）を覆う
様にして全面にCVD（化学反応気相析出）法によるリン
ドープの絶縁酸化膜（22a）を形成し、全面をパッシベ
ーションとすると共に、ゲート電極（17）による段差を
平坦化する為のSOG（スピンオングラス）酸化膜（22b）
を形成する。そして、平坦化した酸化膜（21）上にホト
レジスト膜（23）をスピンオン塗布し、露光・現像する
ことで残存膜（18）に対応する部分に開孔部（24）を有
するホトレジスト膜（23）とする。開孔部（24）は残存
膜（18）パターンと同程度の大きさか若しくは位置合せ
精度を考慮してやや大きな開孔部（24）とする。(F) After that, a phosphorus-doped insulating oxide film (22a) is formed on the entire surface so as to cover the gate electrode (17) and the remaining film (18) by CVD (chemical reaction vapor deposition), and the entire surface is passivated. , SOG (spin-on-glass) oxide film (22b) for flattening the step due to the gate electrode (17)
To form. Then, a photoresist film (23) is applied onto the flattened oxide film (21) by spin-on, and exposed and developed to form a photoresist film (23) having an opening (24) at a portion corresponding to the residual film (18). ). The opening portion (24) has the same size as the pattern of the remaining film (18) or is a slightly larger opening portion (24) in consideration of alignment accuracy.
（ｇ） ホトレジスト膜（23）をマスクとして酸化膜
（21）をエッチングし、残存膜（18）周囲の酸化膜（2
1）を残すようにして残存膜（18）の頭部を露出させ
る。エッチングにはウェット方式による等方エッチング
又はドライ方式による異方又は等方エッチングを用い
る。(G) The oxide film (21) is etched using the photoresist film (23) as a mask, and the oxide film (2) around the residual film (18) is removed.
The head of the remaining film (18) is exposed by leaving 1). For the etching, isotropic etching by a wet method or anisotropic or isotropic etching by a dry method is used.
（ｈ） 続いてポリシリコン（Poly-Si）とシリコン酸
化膜（SiO2）との選択性を利用して、残存膜（18）だけ
をエッチング除去する。エッチングにはHFをベースとし
たウェット方式の他、SF6をエッチングガスとするRIE
（Reactive Ion Etching）によるドライ方式が選択でき
る。RIEでは選択比の高い異方性エッチングができるの
で、極めて正確なエッチング除去ができる。(H) Subsequently, by utilizing the selectivity between polysilicon (Poly-Si) and silicon oxide film (SiO 2 ), only the residual film (18) is removed by etching. In addition to the wet method based on HF for etching, RIE using SF 6 as the etching gas
The dry method by (Reactive Ion Etching) can be selected. Since RIE enables anisotropic etching with a high selection ratio, extremely accurate etching removal can be performed.
（ｉ） 残存膜（18）を除去した後の酸化膜（22）の段
差をマスクとしてリン（Ｐ）等の不純物をイオン注入す
ることにより、ソース領域（21）の真中部分にN+型のコ
ンタクト拡散層（25）を形成する。イオン注入はＮ型拡
散層（20）表面のゲート酸化膜（16）を貫通して行なわ
れ、ソース領域（21）に対して完全なセルフアラインに
より形成できる。(I) An impurity such as phosphorus (P) is ion-implanted using the step of the oxide film (22) after removing the residual film (18) as a mask, so that an N + -type A contact diffusion layer (25) is formed. Ions are implanted through the gate oxide film (16) on the surface of the N type diffusion layer (20) and can be formed by complete self-alignment with the source region (21).
（ｊ） 酸化膜（21）を開孔してN+型コンタクト拡散層
（25）とソース領域（21）の一部を露出し、ソースコン
タクト孔とする。(J) The oxide film (21) is opened to expose a part of the N + type contact diffusion layer (25) and the source region (21) to form a source contact hole.
（ｋ） 全面にAl又は１％Siを含むAl-Siの蒸着によりN
+型コンタクト拡散層（25）とP+型ソース領域（21）の
双方にコンタクトするソース電極（26）を形成し、ポリ
シリコン層からはゲート電極Ｇを取り出し、P+基板（1
1）裏面からドレインとなるべき電極ＤをTi-Ni-Ag等の
蒸着により取り出す。(K) N is formed by vapor deposition of Al or Al-Si containing 1% Si on the entire surface.
A source electrode (26) that contacts both the + type contact diffusion layer (25) and the P + type source region (21) is formed, the gate electrode G is taken out from the polysilicon layer, and the P + substrate (1
1) The electrode D to be the drain is taken out from the back surface by vapor deposition of Ti-Ni-Ag or the like.
このようにして製造された本発明のＰチャンネル型の縦
型MOSFETは、N+型コンタクト拡散層（25）を形成するこ
とでＮ型拡散層（20）とソース電極（21）との良好なオ
ーミックコンタクトが得られ、Ｎ型拡散層（20）の電位
が安定して定まるので、ゲート電極（17）下にチャンネ
ル（反転層）が安定して形成され、従って安定したMOSF
ET動作が得られる。The P-channel vertical MOSFET of the present invention manufactured as described above has a favorable N-type diffusion layer (20) and source electrode (21) by forming the N + -type contact diffusion layer (25). Since an ohmic contact is obtained and the potential of the N-type diffusion layer (20) is stably determined, a channel (inversion layer) is stably formed under the gate electrode (17), and thus a stable MOSF.
ET motion is obtained.
そして本発明の製造方法によれば、残存膜（18）を利用
してN+型コンタクト拡散層（25）をセルフアラインによ
り形成できるので、ゲート電極（17）との、及びソース
領域（21）とのマスク合せ余裕を持たせる必要が無く、
従ってパターンサイズを縮小できる。Further, according to the manufacturing method of the present invention, since the N + type contact diffusion layer (25) can be formed by self-alignment using the residual film (18), the gate electrode (17) and the source region (21) can be formed. It is not necessary to have a mask alignment margin with
Therefore, the pattern size can be reduced.
本発明の第２の実施例は、SOG酸化膜（22b）と等方エッ
チングを利用することによりソース電極（26）の被覆性
を改善するものである。The second embodiment of the present invention is to improve the coverage of the source electrode (26) by utilizing isotropic etching with the SOG oxide film (22b).
すなわち、第１図（ｆ）においてSOG酸化膜（22b）を形
成することにより残存膜（18）上の酸化膜（21）の膜厚
よりソース領域（21）上の酸化膜（21）の膜厚を厚く
し、 第１図（ｇ）において残存膜（18）より大きく酸化膜
（21）をエッチングすることで残存膜（18）頭部が完全
に突出するように露出させ、 第１図（ｈ）において残存膜（18）を除去することによ
り酸化膜（21）に段差を付け、 第１図（ｊ）において前記段差を等方エッチングするこ
とにより、前記段差による膜厚の薄い部分を除去してソ
ースコンタクト孔とし且つ膜厚の厚い部分は前記等方エ
ッチングにより緩らかな段差に形成し、 第１図（ｋ）においてソース電極（26）を形成すること
により、ソース電極（26）の段切れや断線を防止した、
信頼性の高い縦型MOSFETとすることができる。That is, by forming the SOG oxide film (22b) in FIG. 1 (f), the film thickness of the oxide film (21) on the source region (21) is smaller than that of the oxide film (21) on the residual film (18). By increasing the thickness and etching the oxide film (21) larger than the remaining film (18) in FIG. 1 (g), the head of the remaining film (18) is exposed so as to be completely projected, and FIG. In step (h), the residual film (18) is removed to form a step in the oxide film (21), and in step (j) of FIG. 1, the step is isotropically etched to remove the thin portion due to the step. As a source contact hole and a thick film portion, a gentle step is formed by the isotropic etching, and the source electrode (26) is formed in FIG. 1 (k) to form the source electrode (26). Prevents disconnection and disconnection,
It can be a highly reliable vertical MOSFET.
（ト） 発明の効果 以上に説明した如く、本発明によれば、残存膜（18）を
利用することによりゲート電極（17）とN+型コンタクト
拡散層（25）、及びソース領域（21）とN+型コンタクト
拡散層（25）とをセルフアラインにより形成できるの
で、微細化に適した縦型MOSFETの製造方法を提供できる
利点を有する。(G) Effect of the Invention As described above, according to the present invention, by utilizing the residual film (18), the gate electrode (17), the N + -type contact diffusion layer (25), and the source region (21). Since the N + -type contact diffusion layer (25) can be formed by self-alignment, there is an advantage that a vertical MOSFET manufacturing method suitable for miniaturization can be provided.
また、本発明の第２の実施例によれば、ゲート電極（1
7）側面の酸化膜（21）を緩らかな段差に形成できるの
で、ソース電極（26）の段切れや断線を防止した、信頼
性の高い縦型MOSFETを提供できる利点をも有する。Further, according to the second embodiment of the present invention, the gate electrode (1
7) Since the side oxide film (21) can be formed in a gentle step, it also has an advantage that it is possible to provide a highly reliable vertical MOSFET in which disconnection or disconnection of the source electrode (26) is prevented.
第１図（ａ）〜（ｋ）は夫々本発明の製造方法を説明す
る為の断面図、第２図は従来例を説明する為の断面図で
ある。1 (a) to 1 (k) are cross-sectional views for explaining the manufacturing method of the present invention, and FIG. 2 is a cross-sectional view for explaining a conventional example.
Claims (4)
面の一部に不純物を拡散して第２導電型拡散層を形成す
る工程、 前記基体表面にゲート絶縁膜を介してゲート電極を形成
すると共に、前記第２導電型拡散層表面の一部に前記ゲ
ート電極材料を残存膜として残す工程、 前記ゲート絶縁膜と前記残存膜をマスクとしてMOSFETの
チャンネル部分を形成する第２導電型の不純物を拡散す
る工程、 前記ゲート絶縁膜と前記残存膜を再びマスクとしてMOSF
ETのソース領域を形成する第１導電型の不純物を拡散す
る工程、 前記ゲート絶縁膜と前記残存膜を覆うように全面を絶縁
膜で覆う工程、 前記絶縁膜上にホトレジスト膜を形成し、パターニング
して前記残存膜に対応する部分を開孔する工程、 前記ホトレジスト膜をマスクとして前記絶縁膜の膜厚の
一部をエッチングすることにより前記残存膜の頭部を露
出させる工程、 前記絶縁膜と残存膜の選択性により前記残存膜だけをエ
ッチング除去し、その周囲に前記絶縁膜が形成する開孔
を形成する工程、 前記残存膜を除去した後の開孔を選択マスクとして第１
導電型不純物を拡散することにより、前記第２導電型拡
散層の表面に第１導電型高濃度コンタクト拡散層を形成
する工程、 前記絶縁膜を開孔して前記高濃度コンタクト拡散層と前
記ソース領域の一部を露出する工程、 前記高濃度コンタクト拡散層と前記ソース領域の双方に
コンタクトするソース電極を形成する工程とを具備する
ことを特徴とする縦型MOSFETの製造方法。1. A step of diffusing impurities in a part of the surface of a first conductivity type semiconductor substrate to be a drain to form a second conductivity type diffusion layer; forming a gate electrode on the surface of the substrate through a gate insulating film. And leaving the gate electrode material as a residual film on a part of the surface of the second conductive type diffusion layer, the second conductive type impurities forming the channel portion of the MOSFET by using the gate insulating film and the residual film as a mask. Diffusing the gate insulating film and the remaining film again as a mask
A step of diffusing a first conductivity type impurity forming a source region of ET; a step of covering the entire surface with an insulating film so as to cover the gate insulating film and the residual film; forming a photoresist film on the insulating film and patterning; And opening a portion corresponding to the residual film, exposing the head of the residual film by etching a part of the thickness of the insulating film using the photoresist film as a mask, the insulating film and A step of etching and removing only the remaining film according to the selectivity of the remaining film and forming an opening around which the insulating film is formed; a first mask using the opening after removing the remaining film as a selection mask;
Forming a first-conductivity-type high-concentration contact diffusion layer on the surface of the second-conductivity-type diffusion layer by diffusing a conductivity-type impurity; and opening the insulating film to form the high-concentration contact diffusion layer and the source. A method of manufacturing a vertical MOSFET, comprising: exposing a part of a region; and forming a source electrode that contacts both the high-concentration contact diffusion layer and the source region.
部に不純物を拡散して第２導電型拡散層を形成する工
程、 前記基体表面にゲート絶縁膜を介してゲート電極を形成
すると共に、前記第２導電型拡散層表面の一部に前記ゲ
ート絶縁膜材料を残存膜として残す工程、 前記ゲート絶縁膜と前記残存膜をマスクとしてMOSFETの
チャンネル部分を形成する第２導電型の不純物を拡散す
る工程、 前記ゲート絶縁膜と前記残存膜を再びマスクとしてMOSF
ETのソース領域を形成する第１導電型の不純物を拡散す
る工程、 前記ゲート絶縁膜と前記残存膜を覆う様に全面を絶縁膜
で覆い、次いでSOG絶縁膜により表面を平坦化する工
程、 前記絶縁膜上にホトレジスト膜を形成し、パターニング
して前記残存膜に対応する部分を開孔する工程、 前記ホトレジスト膜をマスクとして前記絶縁膜を前記残
存膜より大きな開孔部でエッチングし、前記残存膜の頭
部を露出させる工程、 前記絶縁膜と残存膜の選択性により前記残存膜だけをエ
ッチング除去する工程、 前記残存膜を除去した後の開孔を利用して第１導電型の
不純物を拡散することにより、前記第２導電型拡散層の
表面に第１導電型コンタクト拡散層を形成する工程、 前記ホトレジスト膜をマスクとして前記絶縁膜を等方エ
ッチングすることにより、前記絶縁膜を平坦化すると共
に前記コンタクト拡散層と前記ソース領域の一部を露出
する工程、 前記高濃度拡散コンタクト拡散層と前記ソース領域の双
方にコンタクトするソース電極を形成する工程とを具備
することを特徴とする縦型MOSFETの製造方法。2. A step of diffusing impurities in a part of the surface of a first conductivity type substrate to be a drain to form a second conductivity type diffusion layer, wherein a gate electrode is formed on the surface of the substrate through a gate insulating film. At the same time, a step of leaving the gate insulating film material as a residual film on a part of the surface of the second conductive type diffusion layer, an impurity of the second conductive type forming a channel portion of a MOSFET by using the gate insulating film and the residual film as a mask. Diffusing the gate insulating film and the remaining film again as a mask
Diffusing a first conductivity type impurity forming a source region of ET, covering the entire surface with an insulating film so as to cover the gate insulating film and the remaining film, and then planarizing the surface with an SOG insulating film, A step of forming a photoresist film on the insulating film and patterning to open a portion corresponding to the residual film; etching the insulating film with an opening larger than the residual film by using the photoresist film as a mask; Exposing the head of the film; etching away only the residual film due to the selectivity between the insulating film and the residual film; and removing impurities of the first conductivity type by using the openings after removing the residual film. Forming a contact diffusion layer of the first conductivity type on the surface of the diffusion layer of the second conductivity type by diffusing, and isotropically etching the insulating film using the photoresist film as a mask. Planarizing the insulating film and exposing a part of the contact diffusion layer and the source region, and forming a source electrode contacting both the high-concentration diffusion contact diffusion layer and the source region. A method for manufacturing a vertical MOSFET, comprising:
あり且つ前記ソース電極はアルミニウム又はアルミニウ
ム・シリコンであることを特徴とする請求項第１項又は
第２項に記載の縦型MOSFETの製造方法。3. The vertical MOSFET according to claim 1, wherein the high-concentration contact diffusion layer is an N-type region and the source electrode is aluminum or aluminum silicon. Production method.
前記絶縁膜は酸化膜であり且つ前記残存膜の選択除去は
RIEによる異方性エッチングであることを特徴とする請
求項第１項又は第２項に記載の縦型MOSFETの製造方法。4. The gate electrode material is polysilicon, the insulating film is an oxide film, and the remaining film is selectively removed.
The method of manufacturing a vertical MOSFET according to claim 1 or 2, wherein the etching is anisotropic etching by RIE.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63235827A JPH07101741B2 (en) | 1988-09-20 | 1988-09-20 | Method for manufacturing vertical MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63235827A JPH07101741B2 (en) | 1988-09-20 | 1988-09-20 | Method for manufacturing vertical MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0282628A JPH0282628A (en) | 1990-03-23 |
| JPH07101741B2 true JPH07101741B2 (en) | 1995-11-01 |
Family
ID=16991845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63235827A Expired - Lifetime JPH07101741B2 (en) | 1988-09-20 | 1988-09-20 | Method for manufacturing vertical MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07101741B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5248627A (en) * | 1992-03-20 | 1993-09-28 | Siliconix Incorporated | Threshold adjustment in fabricating vertical dmos devices |
| KR100317090B1 (en) * | 1993-10-26 | 2002-02-19 | 제임스 이. 미러 | Power Train of Four Wheel Drive |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3402867A1 (en) * | 1984-01-27 | 1985-08-01 | Siemens AG, 1000 Berlin und 8000 München | SEMICONDUCTOR COMPONENT WITH CONTACT HOLE |
| JPS62200766A (en) * | 1986-02-28 | 1987-09-04 | Oki Electric Ind Co Ltd | Manufacture of high withstand voltage dsamosfet element |
| JPS62211955A (en) * | 1986-03-12 | 1987-09-17 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH07123127B2 (en) * | 1986-08-19 | 1995-12-25 | 松下電子工業株式会社 | Method for manufacturing MOS field effect transistor |
| JPS63132481A (en) * | 1986-11-22 | 1988-06-04 | Toshiba Corp | Manufacture of field effect transistor |
-
1988
- 1988-09-20 JP JP63235827A patent/JPH07101741B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0282628A (en) | 1990-03-23 |
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