JPH0268951A - Master slice system semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve drive capacity of a circuit block, reduce operation delay time, and enable a cell at a circuit cell part to be used effectively hy providing a circuit cell for constituting a buffer circuit below a wiring channel for using a space outside the circuit block. CONSTITUTION:In a master slice system semiconductor integrated circuit device where a circuit cell row where a plurality of circuit cells which are constituents of the circuit block are arranged and a wiring channel row where wiring for connecting between the circuit blocks are provided alternately, a circuit cell for constituting a buffer cell is placed below the above wiring channel. Then, the buffer circuit is connected to the output part of a circuit block through a wiring where another circuit block exists in the above wiring channel and is connected between the above circuit block and the above other circuit block when load connected to the output part of the above circuit block exceeds a certain value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice semiconductor integrated circuit device, and particularly to a master slice semiconductor integrated circuit device in which a buffer circuit used between circuit blocks is provided under a wiring channel. Related to circuit devices.

[Prior Art] FIG. 4 shows a typical chip configuration of a conventional master slice type semiconductor integrated circuit device. As shown in the figure, in the conventional type, the peripheral part of the semiconductor chip 1 includes a pad 2 for electrical connection with an external circuit, and an input/output for interfacing the external circuit with the internal circuit. Circuit cells 3 are arranged, and an internal circuit region 4 exists inside them.

In the internal circuit area 4, there is a circuit cell row 6 in which circuit cells 5 are arranged in columns, and a wiring channel row 7 for wiring between blocks of a circuit block composed of a plurality of circuit cells.
are arranged alternately. in this way,
Conventionally, no elements were placed under the wiring channel, and the space under the wiring channel was used only for wiring as a completely dead space.

On the other hand, as an improvement to this method, there is a method in which cells that can configure memory cells etc. are also placed under the wiring channel, and some cells under the wiring channel are used for configuring circuit blocks. A method has also been proposed in which cells are formed over the entire internal circuit region and a portion of the cell is used as a wiring channel.

[Problems to be Solved by the Invention] The above-described conventional master slice type semiconductor integrated circuit device has problems when there are no cells under the wiring channel or when the cells there are not used to configure a circuit block. , since there is dead space under the wiring channel, 1
The area efficiency was low, and there were times when there was a shortage of cells to form a circuit block. On the other hand, when an element under a wiring channel is used, the wiring channel is consumed for the connection, resulting in an insufficient number of wiring channels between circuit blocks that are originally required. Therefore, cells arranged under the wiring channel are limited to cells for relatively simple circuit blocks such as memory cells.

Furthermore, in the master slice method, the lengths of wiring between circuit blocks vary, and the magnitude of the load connected to each circuit block also varies. Therefore, in a master slice in which only cells of the same size are arranged, some circuit blocks may lack the ability to drive a load, or the delay time may increase.

[Means for Solving the Problems] The master slice type semiconductor integrated circuit device of the present invention has a circuit cell for configuring a buffer circuit disposed below the wiring channel, and a circuit cell for configuring the buffer circuit by the first layer wiring. After completing the basic wiring, and during the wiring of the circuit block opening in the wiring channel, if necessary,
The buffer circuit is connected to the upper layer wiring.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG.
a) is its plan view, FIG. 1(b) is an equivalent circuit diagram of FIG. 1(a), and FIG. 1(c) and (d) are its plan view.
> is a partial connection diagram. As shown in FIG. 1(a), in the circuit cell section, the gate electrodes 21, 23, P1
A diffusion layer 22 and an N+ diffusion layer 24 are formed;
4 PMOSFETs (hereinafter abbreviated as MP) and 4 NMOSFETs (hereinafter abbreviated as MN) as basic cells
is formed. On the other hand, in the wiring channel section, the gate electrode 4illi25, the P+ diffusion layer 26 and the N+
A diffusion layer 27 is formed, in which four MPs and four MNs for buffer circuits are formed. In the figure, the circles indicate the gate as the pole, the contacts to the P"diffusion layer or the N"diffusion layer, the dotted lines indicate the first layer wiring, the solid lines indicate the second layer wiring, and the dotted lines indicate the third layer wiring. Also, the triangle indicates a through hole connecting the first layer wiring and the second layer wiring (hereinafter referred to as the first through hole), and the double circle indicates the second through hole.
A through hole (hereinafter referred to as a second through hole) connecting the layer wiring and the third layer wiring is shown. Figure 1(a)
The device shown in FIG. 1 constitutes the buffer circuit material 4-input NOR circuit shown in FIG.
Point A in b) is not connected in Fig. 1(a).

Next, the necessity of the buffer circuit will be explained with reference to FIG. In the conventional master slice type integrated circuit device, there is no buffer circuit, and point A shown in FIG. 1(b) is used as the output point of the circuit block, and this point is connected to the wiring in the wiring channel. It was connected to another circuit block.

However, if the load connected to point A is large, a large delay will occur. The magnitude of the load is determined by fan-out and wiring capacitance, and as wiring lengths tend to become longer in recent integrated circuit devices, the load also increases accordingly. FIG. 5 shows the relationship between delay time and load size. Line 1 is
In FIG. 1(b), when there is no buffer, line 2 shows the case with a buffer, and to shows the delay of the buffer itself. In a region with a small load, the delay is smaller if no buffer is provided, but the delay time is smaller if a buffer circuit is provided with the CL as the boundary. Therefore,
In order to shorten the overall delay time, it is necessary to determine the force with which the bath circuit should be connected, depending on the size of the load to be connected, for each circuit block.

The connection or disconnection between the circuit block and the buffer circuit is determined by the first
This can be done by wiring in the C area shown in FIG. That is, when connecting a buffer circuit, the method shown in Fig. 1 (
As shown in c), the output of one circuit block is connected to the buffer circuit via the second through hole, the second layer wiring and the first through hole 10, and the output of the buffer circuit is connected to the buffer circuit through the first through hole 11. and connect it to the output connection point B in the wiring channel. On the other hand, if a sofa circuit is not required, as shown in Figure 1(d),
The output of the circuit block is directly connected to the output connection point B by the third layer wiring 12.

By the way, the boundary point CL in FIG. 5 can be moved by changing the gate width of the MOSFET for the buffer circuit, so in an actual integrated circuit, the dimensions of the FET in the buffer circuit will vary depending on the gate size of the master slice. All you have to do is decide.

According to this embodiment, the wiring of the buffer circuit itself is completed with the first layer wiring, and the connection between the buffer circuit and the circuit block is performed using a part of the peripheral area of the wiring channel. Therefore, the second and third layer interconnects can be freely used as inter-block interconnects in the interconnect channel portion.

Also, whether or not a buffer circuit is used is determined by C in Figure 1(a).
This configuration is convenient for computer processing because it can be performed only by wiring the area, and the output of the circuit block can always be obtained from point B. That is, normally, block circuits with buffer circuits and block circuits without buffer circuits are processed with different block circuit names (labels), but according to this embodiment, this is not necessary. Also,
This can simplify the design process.

Next, another embodiment of the present invention will be described with reference to FIG. Fig. 2(a) is a plan view thereof, and Fig. 2(a) is a plan view thereof.
b) is an equivalent circuit diagram of FIG. 2(a). In this embodiment, the circuit proc has a CMOS at its output.
It has an inverter, and the CMOS inverter of the buffer circuit section is connected in parallel to this inverter. In this way, the effective gate width of the output stage inverter is increased, and the load driving capability of the block circuit inverter is enhanced. If the load is even larger, it is also possible to connect other transistors in the wiring channel section in parallel to further increase the driving capability.

FIG. 3 shows still another embodiment of the present invention, in which a biM-Ra CMO3 (B i CMOS) circuit is used to buffer the wiring channel section. The B1 CMOS buffer has less load dependence of delay time than the CMOS buffer, and is advantageous for speeding up large-scale integrated circuits, but it has a large number of elements, and - for boat fishing, the gate density is not as high as the CMO8. However, if the present invention is applied, the dead space of the wiring channel is effectively utilized, so the high speed of the 1Bi CMOS buffer can be utilized while maintaining the high degree of integration of CMOS.

[Effects of the Invention] As explained above, the present invention provides a load driving circuit under the wiring channel, completes the connection of the load driving circuit mainly by the first layer wiring, and connects the load driving circuit above the first through hole. The following effects can be achieved by adopting a configuration in which the availability of the layer is selected in the wiring process consisting of the layers.

■By using the space outside the circuit block, the driving capacity of the circuit block can be increased and the operation delay time can be shortened.

(2) Since the upper layer wiring of the wiring channel can be freely used as wiring between circuit blocks, even if a buffer circuit is provided under the wiring channel, the degree of freedom in wiring the wiring channel is not reduced.

(2) Since it is no longer necessary to use the cells in the circuit cell section to increase the driving ability of the circuit block, the cells in the circuit cell section can be used effectively.

[Brief explanation of the drawing]

FIG. 1 (a> is a plan view showing one embodiment of the present invention;
Figure (b) is its equivalent circuit diagram, Figure 1 (C) and (d)
is a partial connection diagram of FIG. 1(a), FIG. 2(a) is a plan view of another embodiment of the present invention, FIG. 2(b) is its equivalent circuit diagram, and FIG. FIG. 4 is a circuit diagram showing still another embodiment of the present invention, FIG. 4 is a plan view of the conventional example, and FIG. 5 is an explanatory diagram of the operation of the present invention. 21.23.25...Gate electrode, 22.26.
...P+ diffusion layer, 24.27...N+ diffusion layer, M
P...PMO3FET, MN...NMO8FET
.

Claims (1)

[Claims] In a master slice type semiconductor integrated circuit device, circuit cell rows in which a plurality of circuit cells constituting a circuit block are arranged and wiring channel rows in which wirings connecting between circuit blocks are arranged alternately. Circuit cells that can constitute a buffer circuit are arranged under the wiring channel, and the buffer circuit connects the output section of a certain circuit block to another circuit block via the wiring existing in the wiring channel. and is connected between the certain circuit block and the other circuit block when the load connected to the output part of the certain circuit block is equal to or higher than a certain value. A master slice semiconductor integrated circuit device characterized by: