JPS62188340A - Master slice type semiconductor integrated circuit device - Google Patents

Master slice type semiconductor integrated circuit device

Info

Publication number
JPS62188340A
JPS62188340A JP3116186A JP3116186A JPS62188340A JP S62188340 A JPS62188340 A JP S62188340A JP 3116186 A JP3116186 A JP 3116186A JP 3116186 A JP3116186 A JP 3116186A JP S62188340 A JPS62188340 A JP S62188340A
Authority
JP
Japan
Prior art keywords
master slice
semiconductor integrated
circuit
integrated circuit
type semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3116186A
Other languages
Japanese (ja)
Inventor
Jun Takayama
純 高山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3116186A priority Critical patent/JPS62188340A/en
Publication of JPS62188340A publication Critical patent/JPS62188340A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To form a large-scale logical circuit containing a circuit requiring a large load driving capability by a method wherein a region exclusively used for buffer circuit is provided. CONSTITUTION:A buffer circuit 4 is formed on the center part of a master slice chip 1 in the process to be performed before a wiring process, it is used as the region 5 to be exclusively used for a buffer circuit, and a fundamental cell 6 is formed on the upper and the lower parts of the region 5 to be exclusively used for the buffer circuit. As above-mentioned, the buffer circuit 4 can be used for the circuit on which a large load driving capability is required.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は大規模な論理ゲート回路金形成し得るマスター
スライス型半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice type semiconductor integrated circuit device capable of forming large scale logic gate circuits.

〔従来の技術〕[Conventional technology]

通常、短納期でＬＳＩ化する論理ゲート回路には、マス
タースライス方式のＬＳＩが利用される事が多い。Normally, master slice type LSIs are often used for logic gate circuits that can be converted into LSIs in a short period of time.

従来、このマスタースライス型半導体集積回路装置は、
第２図に示す様なチップレイアウトとなっていた。第２
図において、マスタースライスチップ１のセル領域３の
内部に多数の基本セル６を配線工程以前の工程で形成し
ておき％次いで配線工程以降の工程でそれぞれの用途に
応じて回路機能を切り挨えて使用していた。Conventionally, this master slice type semiconductor integrated circuit device
The chip layout was as shown in Figure 2. Second
In the figure, a large number of basic cells 6 are formed inside the cell region 3 of the master slice chip 1 in a process before the wiring process, and then the circuit functions are cut according to the application in the process after the wiring process. I was using it.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

この様な装置では１回路規模が大きくなシ多数の回路全
駆動するバッファー回路が必要となった場合、基本セル
の負荷駆動能力の限界による制限を受けＬＳＩ化が実現
出来ない欠点がある。Such a device has the disadvantage that the scale of one circuit is large, and if a buffer circuit for driving all of a large number of circuits is required, it cannot be implemented as an LSI due to the limit of the load driving ability of the basic cell.

本発明の目的は、上記欠点を解決し大きな負荷駆動能力
を必要とする回路金倉む大規模な論理回路を形成し得る
マスタースライス型半導体集積回路装置を提供する事に
ある。SUMMARY OF THE INVENTION An object of the present invention is to provide a master slice type semiconductor integrated circuit device capable of solving the above-mentioned drawbacks and forming a large-scale logic circuit including circuits requiring large load driving capability.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は％あらかじめ形成された基本セルの配線工程を
切り換える事により任意の論理ゲート回路を形成する半
導体集積回路装置において、基本セル領域とバック了−
回路専用領域を備えて構成されるマスタースライス型半
導体集積回路装置である。The present invention relates to a semiconductor integrated circuit device in which an arbitrary logic gate circuit is formed by switching the wiring process of pre-formed basic cells.
This is a master slice type semiconductor integrated circuit device configured with a dedicated circuit area.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例のチップレイアウト図である
。本実施例では、配線工程以前の工程でバッファー回路
４をマスタースライスチップ１の中央部に形成しバッフ
ァー回路専用領域５とし。FIG. 1 is a chip layout diagram of an embodiment of the present invention. In this embodiment, a buffer circuit 4 is formed in the center of the master slice chip 1 in a process before the wiring process, and a buffer circuit dedicated area 5 is formed.

基本セル６はバッファー回路専用領域５の上方部。The basic cell 6 is located above the buffer circuit exclusive area 5.

下方部に形成する。次いで配線工程にて必要な機能を持
たせた回路をそれぞれの領域に形成する。Formed in the lower part. Next, in a wiring process, circuits with necessary functions are formed in each region.

以上の様に大きな負荷駆動能力が要求される回路にはバ
ッファー回路４が使用可能となる。As described above, the buffer circuit 4 can be used in a circuit that requires a large load driving capability.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれは、バッファー回路専
用領域を設けた事ＶＣよシ、大きな負荷部＠能力を必要
とする回路を含む大規模な論理回路全形成する事が可能
である。As explained above, according to the present invention, it is possible to form all large-scale logic circuits including circuits requiring a large load section @capacity in addition to the VC by providing an area exclusively for buffer circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明によるマスタースライス型半導体集積回
路装置の一実施例金示すテップレイアウト図、第２図は
従来のマスタースライス型半導体集積回路装置のチップ
レイアウト図である。 １・・・・・・マスタースライスチップ、２・・・・・
・電極ハツト、３・・・・・・セルｔｄ［，４・・・・
・・バッフ了−回路。 ５・・・・・・バッファー回路専用領域、６・・・・・
・基本セル。 ＼　９　　つ　　　　も ＼　　へ　　　　つFIG. 1 is a chip layout diagram showing an embodiment of a master slice type semiconductor integrated circuit device according to the present invention, and FIG. 2 is a chip layout diagram of a conventional master slice type semiconductor integrated circuit device. 1... Master slice chip, 2...
・Electrode hat, 3... Cell td [, 4...
...Buffer complete - circuit. 5... Buffer circuit dedicated area, 6...
・Basic cell. ＼ Nine too＼ He Tsu

Claims (1)

【特許請求の範囲】[Claims] あらかじめ形成された基本セルの配線工程を切り換える
事により任意の論理ゲート回路を形成する半導体集積回
路装置において、基本セル領域とバッファー回路専用領
域を備えた事を特徴とするマスタースライス型半導体集
積回路装置。A master slice type semiconductor integrated circuit device that forms an arbitrary logic gate circuit by switching the wiring process of pre-formed basic cells, the device comprising a basic cell area and a dedicated buffer circuit area. .
JP3116186A 1986-02-14 1986-02-14 Master slice type semiconductor integrated circuit device Pending JPS62188340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3116186A JPS62188340A (en) 1986-02-14 1986-02-14 Master slice type semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3116186A JPS62188340A (en) 1986-02-14 1986-02-14 Master slice type semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS62188340A true JPS62188340A (en) 1987-08-17

Family

ID=12323719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3116186A Pending JPS62188340A (en) 1986-02-14 1986-02-14 Master slice type semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS62188340A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0268951A (en) * 1988-09-03 1990-03-08 Nec Corp Master slice system semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0268951A (en) * 1988-09-03 1990-03-08 Nec Corp Master slice system semiconductor integrated circuit

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