JPS5965451A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize a master slice LSI without leaving almost all unused region within the one master chip and remarkably improve yield of chip by including two or more logic circuits having independent functions within only one chip. CONSTITUTION:A plurality of independent logic circuits are formed within one master chip as many as the gates of master chip (a number of basic cells included in one chip) are used sufficiently. On the occasion of executing a die sort test of a composite logic function LSI obtained, if one logic function is not normal, it is not considered as defective. The test is further conducted for the other functions. When at least one logic function is normal, such LSI is considered as normal. Such LSI is cut as the final LSI from the wafer and it is built into a package for actual use.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit (hereinafter abbreviated as LSI), and in particular to a master slice type LSI.
Regarding.

[Technical advantages of the invention and its problems]

The master slicing method is a method in which a large number of basic cells, which usually consist of multiple elements (including active elements such as transistors and passive elements such as resistors), are integrated in a matrix in one semiconductor chip. A master chip is formed on a semiconductor wafer, and the elements in the basic cell are connected using a wiring mask according to the developed product to realize a logic circuit with the desired logic function as appropriate [7. They are connected to complete the final LSI.

Generally, a plurality of types of master chips are prepared in stages depending on the number of basic cells included in one chip (for convenience, this number will be referred to as the number of gates hereinafter). Representative examples of this master chip OR) variety are shown in the table below. The table shows the number of input/output pads and chip→J
- Indicates is.

The use of these master chips according to conventional technology is as follows:
First, from the logic circuit of the final LSI, the number of basic cells (number of gates) to be used when this is realized with the basic cells of the master slice is calculated.

Next, a master chip with the minimum number of gates is selected to allow use of that number of gates, a wiring pattern is designed to match this, and the final LSI is realized. For example, suppose that the number of gates in two logic circuits is calculated to be 4.5 gates and 15 gates, and if the most important master chip for these is selected from the table above, each has 6.5 gates and 15 gates.
The master chip of gate 1 and gate 2 is selected.

That is, the minimum master chips that can realize 4.5K and 1.5K gates are 6 and 2 gates, respectively. In this case, an unused area for 1.5 gates will be generated in the gate master chip at 6, and an unused area for 0.5 gates will be generated in the gate mask-handle at 2. A region will be generated. This area is not only unnecessary for the circuit, but also increases the chip size unnecessarily compared to the originally required device area, thus reducing the number of chips obtained from one wafer (chip gross). It is also a harmful area.

[Purpose of the invention]

This invention solves the following problems without increasing the design effort.
In other words, there is almost no occurrence of unused areas in the master chip. 1-1 Most of the chips that were previously discarded as defective are now used in 1K products and 17.
% product circuit device.

[Summary of the invention]

In this invention, the logic circuit formed in one master chip is not limited to one circuit, but is formed by combining multiple mutually independent logic circuits until the number of gates of the master chip is used for the part. do. Thus obtained A
When performing a die sort test on a complex logic function LSI, even if one logic function does not operate normally,
Don't immediately mark it as defective, test other logic functions, and if at least one logic function works normally,
This can be used as a non-defective product, cut from the wafer as a final LSI with logic functions that operate normally, and incorporated into a computer, etc.

[Effect of the invention] By doing so, a master slice LSI can be realized without leaving almost any unnecessary and harmful unused area in one master chip17, and the yield of the chip can also be significantly improved. can. Also,
It is possible to realize an LSI that is more suitable for automation in the design process.

[Embodiments of the invention]

Let us take up an example of realizing the gate logic circuit in 4, 5, and 1.5. In this case, the optimal master chip to simultaneously realize a 4.5K and 1.5K gate logic circuit is a 6K gate chip, and if this is used, there will be no unused portion left in the master chip. Become. Therefore, the above problems are completely solved. Recently, the master slice LSI design method has become completely automated, and the connection information of a logic circuit is input into a computer, and the output is a wiring mask pattern that realizes the circuit. This is common. In this case, as shown in the figure, in order to obtain the circuit connection data 3 of the gate 6, which is the summation of the two circuit connection information 1 and 2 of the gate 4.5 and the gate 1.5, these Since the circuits are independent of each other, there is no need to modify the circuit connection data, and it is only necessary to change both once. Therefore, 4.5R and 1.
Rather than performing computer processing twice in 5th and 5th gates, only one time in 6th gates is required, which reduces the number of processes that require human hands during cutting, and reduces the number of errors.

Considering the yield further, if we assume that the yield of -1 gate (l) is α (0 < α × 1) as usual for master slice type LSI, then t is 4.5 for LSI using gates. -1: +The yield I) is α4.
5 I) If you achieve a gate master tube of 4.5 with a gate master tube of 6I with the conventional method of using force 1', the remaining ratio (1-α4・5K) will be unsuitable. Tipping was occurring.

However, in this invention, the conventional defective bone (1-α4°5
Since α1°5 of K) can be used as a good product, the total (α4°5→−(1−α))
Good products can be obtained at a ratio of α). Now α-0,999
85, α = 0.51, and the conventional method is 4.
In order to realize an LSI of 5.5K, approximately half of the 6K masters would be discarded as defective, but in this invention, (α4°5, + (1-α4°5K)α1・
5K) becomes 0.90 - completely defective, which decreases to about 1-0%.

In order to perform a die sort test on this LSI, it is best to perform a die sort test on the complex logic circuits, starting with the circuits with the smallest gate scale and then proceeding to the circuits with the smallest gate scale. In the example written in nil, first test the gate circuit in 4.5, and if α=0.99985 -
51% of good products were obtained. Next, the gate circuits of the remaining 1149% of the parts are tested in step 1.5, and α -80% of them are determined to be good products, and 20% are determined to be completely defective products. Thus, the LS of the gate is 4.5, which is 51%.
It is determined that the gate LSI is completely defective at 1.5 of I, 39%, and 10%.

In general, T,SI using the manutar slice method is aimed at producing a large variety of LSIs in small quantities, and most of the design process is fully automated. This invention takes advantage of the characteristics of the master slice method, and furthermore,
Suitable for automation T7, suitable for low-volume, high-mix LSI 1. It is something that

[Brief explanation of drawings]

The figure shows an example of a rough method for creating computer input data for a complex logic circuit according to the present invention.

Claims (1)

[Claims] Mapping a basic cell consisting of multiple active elements on a semiconductor chip)
In a master slice type semiconductor integrated circuit device that is integrated into an IJ rack and realizes a desired logic function by designing a wiring pattern, two or more logic circuits with independent functions are installed in one chip. A semiconductor integrated circuit device comprising: