JPH026683Y2 - - Google Patents
Info
- Publication number
- JPH026683Y2 JPH026683Y2 JP13625884U JP13625884U JPH026683Y2 JP H026683 Y2 JPH026683 Y2 JP H026683Y2 JP 13625884 U JP13625884 U JP 13625884U JP 13625884 U JP13625884 U JP 13625884U JP H026683 Y2 JPH026683 Y2 JP H026683Y2
- Authority
- JP
- Japan
- Prior art keywords
- logic
- gate
- logic gate
- gates
- boolean expression
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000014509 gene expression Effects 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Logic Circuits (AREA)
- Image Processing (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13625884U JPH026683Y2 (cs) | 1984-09-10 | 1984-09-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13625884U JPH026683Y2 (cs) | 1984-09-10 | 1984-09-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6151555U JPS6151555U (cs) | 1986-04-07 |
| JPH026683Y2 true JPH026683Y2 (cs) | 1990-02-19 |
Family
ID=30694722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13625884U Expired JPH026683Y2 (cs) | 1984-09-10 | 1984-09-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH026683Y2 (cs) |
-
1984
- 1984-09-10 JP JP13625884U patent/JPH026683Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6151555U (cs) | 1986-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0270219A2 (en) | Reduced parallel EXCLUSIVE OR and EXCLUSIVE NOR gate | |
| JPS595349A (ja) | 加算器 | |
| JPH0531769B2 (cs) | ||
| JPH035095B2 (cs) | ||
| JPS6361327A (ja) | 加算器 | |
| US4918640A (en) | Adder cell having a sum part and a carry part | |
| JPH026683Y2 (cs) | ||
| US4349888A (en) | CMOS Static ALU | |
| US4675838A (en) | Conditional-carry adder for multibit digital computer | |
| EP0266866B1 (en) | Dual mode-increment/decrement n-bit counter register | |
| US4739195A (en) | Mosfet circuit for exclusive control | |
| JPH0476133B2 (cs) | ||
| JPS5814691B2 (ja) | 2進加算回路 | |
| US5670900A (en) | Mask decoder circuit optimized for data path | |
| JP3137629B2 (ja) | 桁上げ‐セーブ算術演算機構に対する加算器セル | |
| JPH0262057B2 (cs) | ||
| JP2569765B2 (ja) | 信号処理集積回路装置 | |
| JPH07118643B2 (ja) | データを処理するための回路網 | |
| JPH0377537B2 (cs) | ||
| JP2563234B2 (ja) | インストラクションレジスタ | |
| JPS62166424A (ja) | ワレスのトリ−回路 | |
| JPS61145930A (ja) | 相補型mosトランジスタ出力回路 | |
| JPS6129018B2 (cs) | ||
| JPH05216818A (ja) | バス回路 | |
| JPH0646379B2 (ja) | 桁上げ論理回路 |