JPH026683Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a digital arithmetic circuit composed of a plurality of logic gates, and particularly to a digital arithmetic circuit suitable for digital image processing and the like.

[Prior art] For example, in the field of digital image processing, image information A and image information B are processed by (i) passing A, (ii) passing B, (iii) AND operation of A and B, (iv ) OR operation between A and B, (v) exclusive OR (EXOR) operation between A and B,
(vi) One of the six operations of multiplex operations A and B is selectively executed by using control bits. As a conventional structure to achieve this,
There is a system in which logic gates corresponding to the operations (i) to (vi) above are prepared individually, and one logic gate is selected by a 6:1 multiplexer. However, this configuration requires a large number of logic gates, which is undesirable in terms of space within the LSI and cost.

[Summary of the idea]

The purpose of this invention is to realize a digital arithmetic circuit that can perform all the operations (i) to (vi) above using a small number of logic gates.

According to this invention, all operations (i) to (vi) described above can be selectively performed preferably with only nine gates. Which operation to select is determined by 4-bit control signals S1, S2, S3, and S4.

〔Example〕

In FIG. 1, A and B are a pair of logic input terminals (signals), and S1, S2, S3, and S4 are logic control terminals (signals). G1, G2, G3, G4, G5
is a logic gate circuit, among which G1, G2,
Since the input terminals of the four gates G4 and G5 are three terminals, the total number of gates is 2×4+1=9
It can be counted as 1. First, gate G1 is X1=・
It is connected to output a signal corresponding to the Boolean expression S2·B. Next, gate G2 is X2=
It is connected to output signals corresponding to the Boolean expressions S1, A, and X1. Gate G3 is X3=
It is connected to output a signal corresponding to the Boolean expression S4・1. Gate G4 is X4=1・
It is connected to output a signal corresponding to the Boolean expression B·S3. Gate G5 is X5=2+3
It is connected to output a signal corresponding to the Boolean expression +4, and this X5 becomes the output from the output terminal O.

[Effect]

The logic circuit shown in Figure 1 consists of (i) path A, (ii) path B
path, (iii) AND of A and B, (iv) OR of A and B, (v) A
and (vi) multiplexing of A and B can be selectively performed. Therefore, these will be explained in order.

(i) Path of A In this case, set the control terminals as S1=1, S2=0, and S3=0 (S4 is irrelevant). Then, X1=1,
X2=, X3=1, X4=1, so X5=A+0
+0=A (ii) Path of B In this case, set the control terminals as S1=0, S2=0, S3=1 (S4 is irrelevant). Then, X1=1,
X2=1, X3=1, X4= so X5=0+0
+B=B (iii) AND of A and B In this case, S1=0, S2=1, S3=0, S4=0
and set the control terminal. Then, X1=...
X2=1, X3=・, X4=1, then X5=0
+A・B+0=A・B (iv) OR of A and B In this case, set the control terminals as S1=1, S2=0, and S3=1 (S4 is irrelevant). Then, X1=1,
X2=, X3=1, X4=, so X5=A+0
+B=A+B (v) Exclusive OR (EXOR) of A and B In this case, set the control terminal as S1=S2=S3=S4=1. Then, X1=・, X2=A・
A・B, X3=1, X4=...B becomes X5=
A...+0+B...=A.+.B (vi) Multiplexing (MUX) of A and B In this case, set the control terminals as S1=Z, S2=0, and S3=(S4 is irrelevant). Z is a control bit; if Z=1, A is output; if Z=0, B is output. Then, 1=1, X2=・
A, X3=1, X4=B・So X5=A・Z+
0+B・=A・Z+B・ These results are summarized as shown in Figure 2. In addition, in FIG. 2, the "X" mark indicates that there is no relation.

Although the circuit shown in FIG. 1 uses NAND gates with negative logic, an equivalent circuit using AND gates with positive logic can also be constructed. In that case,
The output of each gate is X1=A・B・S2, X2=A・
X1・S1, X3=X1・4, X4=B・1・S4, X5
=X2+X3+X4. Also, according to de Morgan's theorem, gates G1, G2, G4 and gate G5 are equivalent, and gate G3 is a normal OR without inversion.
Equivalent to gate. Of course, the present invention also includes these equivalent circuits.

[Effect of idea]

As described above, according to the configuration of this invention, all six types of operations (Fig. 2) normally required for two inputs A and B can be selectively realized using only nine gates. When this logic circuit is applied to an LSI, it has the effect of significantly reducing the number of gates.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the arrangement of logic gates in the digital arithmetic circuit of the present invention, and FIG. 2 shows control signals S1 to S to be set to select each operation.
4 is a diagram showing state No. 4. FIG. S1, S2, S3, S4...control terminals, A, B
...Input terminal, G1, G2, G3, G4, G5...
...Logic gate.

Claims (1)

[Claims for Utility Model Registration] Four control terminals S1, S2, S3, S4 each taking a logic value of "1" or "0" and a pair of inputs each taking a logic value of "1" or "0" Terminals A and B, one output terminal O, a first logic gate for generating a signal expressed by the Boolean expression X1=・2・, and a signal expressed by the Boolean expression X2=1・・1. a second logic gate for generating a signal expressed by the Boolean expression X3=4・1, and a third logic gate for generating a signal expressed by the Boolean expression X4=1...3. a fourth logic gate, and a fifth logic gate for generating a signal expressed by the Boolean formula X×5=2+3+4 and outputting it to the output terminal O.
A digital arithmetic circuit comprising: a logic gate;