JPH0263277B2 - - Google Patents
Info
- Publication number
- JPH0263277B2 JPH0263277B2 JP57006009A JP600982A JPH0263277B2 JP H0263277 B2 JPH0263277 B2 JP H0263277B2 JP 57006009 A JP57006009 A JP 57006009A JP 600982 A JP600982 A JP 600982A JP H0263277 B2 JPH0263277 B2 JP H0263277B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- control signal
- mosfet
- ram
- input buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
Landscapes
- Static Random-Access Memory (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57006009A JPS58125291A (ja) | 1982-01-20 | 1982-01-20 | Mosスタテイツク型ram |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57006009A JPS58125291A (ja) | 1982-01-20 | 1982-01-20 | Mosスタテイツク型ram |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3294149A Division JP2631925B2 (ja) | 1991-11-11 | 1991-11-11 | Mos型ram |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58125291A JPS58125291A (ja) | 1983-07-26 |
JPH0263277B2 true JPH0263277B2 (enrdf_load_stackoverflow) | 1990-12-27 |
Family
ID=11626715
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57006009A Granted JPS58125291A (ja) | 1982-01-20 | 1982-01-20 | Mosスタテイツク型ram |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58125291A (enrdf_load_stackoverflow) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60103585A (ja) * | 1983-11-11 | 1985-06-07 | Nec Corp | Cmosメモリ回路 |
JPH0795395B2 (ja) * | 1984-02-13 | 1995-10-11 | 株式会社日立製作所 | 半導体集積回路 |
EP0404013B1 (en) * | 1989-06-19 | 1995-12-13 | Nec Corporation | Semiconductor memory device with an improved write control circuit |
JP3057710B2 (ja) * | 1990-04-27 | 2000-07-04 | 日本電気株式会社 | 半導体メモリ装置 |
JPH07122996B2 (ja) * | 1991-02-13 | 1995-12-25 | 株式会社日立製作所 | 半導体集積回路 |
KR940007639B1 (ko) * | 1991-07-23 | 1994-08-22 | 삼성전자 주식회사 | 분할된 입출력 라인을 갖는 데이타 전송회로 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5345939A (en) * | 1976-10-07 | 1978-04-25 | Sharp Corp | Ram circuit |
JPS5437544A (en) * | 1977-08-29 | 1979-03-20 | Sharp Corp | Mos static random access memory |
JPS5835783A (ja) * | 1981-08-24 | 1983-03-02 | Fujitsu Ltd | 半導体メモリ |
-
1982
- 1982-01-20 JP JP57006009A patent/JPS58125291A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS58125291A (ja) | 1983-07-26 |
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