JPH0262064B2 - - Google Patents

Info

Publication number
JPH0262064B2
JPH0262064B2 JP3190385A JP3190385A JPH0262064B2 JP H0262064 B2 JPH0262064 B2 JP H0262064B2 JP 3190385 A JP3190385 A JP 3190385A JP 3190385 A JP3190385 A JP 3190385A JP H0262064 B2 JPH0262064 B2 JP H0262064B2
Authority
JP
Japan
Prior art keywords
signal
reference value
strobe signal
circuit
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3190385A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61191135A (ja
Inventor
Hideaki Minami
Akihiro Kozuki
Mitsumasa Ootani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tsubakimoto Chain Co
Original Assignee
Tsubakimoto Chain Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsubakimoto Chain Co filed Critical Tsubakimoto Chain Co
Priority to JP60031903A priority Critical patent/JPS61191135A/ja
Publication of JPS61191135A publication Critical patent/JPS61191135A/ja
Publication of JPH0262064B2 publication Critical patent/JPH0262064B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP60031903A 1985-02-19 1985-02-19 2値信号の読取回路 Granted JPS61191135A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60031903A JPS61191135A (ja) 1985-02-19 1985-02-19 2値信号の読取回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60031903A JPS61191135A (ja) 1985-02-19 1985-02-19 2値信号の読取回路

Publications (2)

Publication Number Publication Date
JPS61191135A JPS61191135A (ja) 1986-08-25
JPH0262064B2 true JPH0262064B2 (enrdf_load_html_response) 1990-12-21

Family

ID=12343958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60031903A Granted JPS61191135A (ja) 1985-02-19 1985-02-19 2値信号の読取回路

Country Status (1)

Country Link
JP (1) JPS61191135A (enrdf_load_html_response)

Also Published As

Publication number Publication date
JPS61191135A (ja) 1986-08-25

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