JPH025590A - Multilayer interconnection substrate - Google Patents
Multilayer interconnection substrateInfo
- Publication number
- JPH025590A JPH025590A JP15716488A JP15716488A JPH025590A JP H025590 A JPH025590 A JP H025590A JP 15716488 A JP15716488 A JP 15716488A JP 15716488 A JP15716488 A JP 15716488A JP H025590 A JPH025590 A JP H025590A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- upper conductor
- viahole
- via hole
- lower conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 10
- 239000004020 conductor Substances 0.000 claims abstract description 47
- 229910000679 solder Inorganic materials 0.000 abstract description 16
- 239000000463 material Substances 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 4
- 238000007598 dipping method Methods 0.000 abstract 1
- 206010011732 Cyst Diseases 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は各種電子機器等に用いることが出来る多層配線
基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a multilayer wiring board that can be used in various electronic devices.
従来の技術
従来のセラミックや樹脂を絶縁基板とする多層配線基板
は、第３図及び第４図で示す様に絶縁基板１６の上に下
部導体１２が形成さ゛れ、更に絶縁層１６．上部導体１
１を形成して多層化されるものである。この多層配線基
板は、下部導体１２と上部導体１１とを電気的に接続す
るためにビアホー／１／１７を有１〜でいる。下部導体
１２と上部導体１１とをビアホール１７を通じて電気的
に接続１〜多層基板として機能させる方法と［，２ては
、上部導体１１の形成時に同一材料を用いて一体的に形
成する場合もあるが、多層基板の形成後に別の手段、例
えば半田材１３を用いて部品実装時に導通短絡すること
もたびたび用いられる。2. Description of the Related Art In a conventional multilayer wiring board using ceramic or resin as an insulating substrate, a lower conductor 12 is formed on an insulating substrate 16, as shown in FIGS. 3 and 4, and an insulating layer 16. Upper conductor 1
1 and is multilayered. This multilayer wiring board has a via hole/1/17 for electrically connecting the lower conductor 12 and the upper conductor 11. The lower conductor 12 and the upper conductor 11 are electrically connected through the via hole 17 1 - A method of functioning as a multilayer board [, 2] In some cases, the upper conductor 11 is formed integrally using the same material. However, after forming a multilayer board, another means, for example, using solder material 13, is often used to conduct and short circuit during component mounting.
発明が解決しようとする課題
この様に構成された従来の多層配線基板に対１〜て、ビ
アホーＡ・１７内に半田材１３を供給充填し、す７０−
やデイツプ等の手段を用いて上部導体１１と下部導体１
２とを半田接続しようとすると、ビアホール接続ランド
より引き出される部分の、、に部導体が太い場合、引き
出される上部導体の半田１／シストのかか−）でいない
導体すなわちビアホール接続ランド１８の面積だけビア
ホール接続ランドの面積が増大する。この傾向は半田レ
ジスト１４の位置ずれが太きければ大きい程顕著となる
。Problems to be Solved by the Invention Regarding the conventional multilayer wiring board configured as described above, solder material 13 is supplied and filled into the via hole A 17, and step 70-
The upper conductor 11 and the lower conductor 1 are
2, if the part of the conductor that is drawn out from the via hole connection land is thick, the area of the conductor that is not covered by the solder 1/the heel of the cyst of the upper conductor that is drawn out, that is, the area of the via hole connection land 18. The area of the via hole connection land increases. This tendency becomes more pronounced as the positional deviation of the solder resist 14 increases.
このため、ビアホール接続ランド１８の面積の大きい方
へ半田材の表面張力によって半田材が引っばられ、上部
導体と下部導体との接続が不安定となり、信頼性の確保
が困難となる課題を有していた。Therefore, the surface tension of the solder material causes the solder material to be pulled toward the larger area of the via hole connection land 18, making the connection between the upper conductor and the lower conductor unstable, making it difficult to ensure reliability. Was.
課題を解決するための手段
本発明はかかる課題を解決するため、ビアホール接続ラ
ンドより引き出される部分の上部導体をビアホール接続
ランドの幅よりも細くするという構成を備えたものであ
る。Means for Solving the Problems In order to solve the problems, the present invention has a structure in which the portion of the upper conductor drawn out from the via hole connection land is made thinner than the width of the via hole connection land.
作用
本発明は上記の構成により、ビアホール接続ランドより
引き出される部分の上部導体によるビアホール接続ラン
ドの増大する面積は非常に少なくなり、半田材は均一に
上部導体と下部導体に導通短絡できる。According to the above-described structure of the present invention, the area of the via hole connecting land increased by the portion of the upper conductor drawn out from the via hole connecting land is extremely small, and the solder material can uniformly conduct and short-circuit the upper conductor and the lower conductor.
実施例
第１図は本発明の多層配線基板を示し、第２図は第１図
の人−人′断面図である。６はアルミナやガラスエポキ
シ等からなる絶縁基板であり、その上に下部導体２を形
成し、上部導体１と下部導体２を接続する位置に窓を開
けた絶縁層６をはさんで上部導体１を形成し、上部導体
の上に半田レジストを形成する。ビアホール接続ランド
８に半田材３を供給充填し、デイツプやりフロー等の手
段を用いて上部導体１と下部導体２を半田接続する。こ
の時、ビアホール接続ランド８から引き出される部分の
上部導体１はビアホール接続ランド８の幅よりも細くな
っているので、上部導体によるビアホール接続ランド８
の面積増大が少ないため、半田材３の表面張力により半
田材３が引きよせられる影響は少ない。このために安定
したビアホール接続が得られ、高信頼性を確保すること
が可能となる。Embodiment FIG. 1 shows a multilayer wiring board according to the present invention, and FIG. 2 is a cross-sectional view of FIG. 6 is an insulating substrate made of alumina, glass epoxy, etc., on which the lower conductor 2 is formed, and the upper conductor 1 is sandwiched between the insulating layer 6 with a window opened at the position where the upper conductor 1 and the lower conductor 2 are connected. A solder resist is formed on the upper conductor. The solder material 3 is supplied and filled into the via hole connection land 8, and the upper conductor 1 and the lower conductor 2 are connected by soldering using means such as dip or flow. At this time, since the portion of the upper conductor 1 drawn out from the via hole connection land 8 is narrower than the width of the via hole connection land 8, the via hole connection land 8 by the upper conductor
Since the increase in area is small, the influence of the solder material 3 being pulled together by the surface tension of the solder material 3 is small. Therefore, stable via hole connections can be obtained and high reliability can be ensured.
発明の効果
以上のように本発明によれば、非常に簡単な構成を用い
て、安定なビアホールの接続状態が得られることがら、
工業上極めて有益なものである。Effects of the Invention As described above, according to the present invention, a stable via hole connection state can be obtained using a very simple configuration.
It is extremely useful industrially.
第１図は本発明の一実施例における多層配線基板を示す
平面図、第２図は第１図のムー人′断面図、第３図は従
来の多層配線基板を示す平面図、第４図は第３図のＢ−
Ｂ’断面図である。
１・・・・・・上部導体、２・・・・・・下部導体、３
・・・・・・半田材、４・・・・・・半田レジスト、５
・・・・・・絶縁層、６・・・・・・絶縁基板、７・・
・・・・ビアホール、８・・・・・・ビアホール接続ラ
ンド。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第
図
２−・
−ｍ−
７−・
−ｍ−
上部−Ｓ体
下部導体
や田社
↑田しジスト
杷縛層
＆！！Ｍ１慕襞
ヒ ７ ホ − ル
ヒアホール停現ラフト
第
図FIG. 1 is a plan view showing a multilayer wiring board according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the multilayer wiring board shown in FIG. 1, FIG. 3 is a plan view showing a conventional multilayer wiring board, and FIG. is B- in Figure 3.
It is a B' sectional view. 1... Upper conductor, 2... Lower conductor, 3
...Solder material, 4...Solder resist, 5
...Insulating layer, 6...Insulating substrate, 7...
... Via hole, 8... Via hole connection land. Name of agent: Patent attorney Toshio Nakao and one other person Figure 2-・-m- 7-・-m- Upper-S-body lower conductor and Tashiya ↑ Tashist binding layer &! ! M1 Mo-hi-hi 7 Hole - Diagram of the raft showing the hole
Claims (1)
前記下部導体部の一部を露出させた状態で前記下部導体
部と前記絶縁基板との上に配された絶縁層と、前記下部
導体部の上の前記絶縁層の上に配されたビアホール接続
ランドと、前記絶縁層の上に配され前記ビアホール接続
ランドと接続された上部導体部とを備え、前記ビアホー
ル接続ランドと接続される前記上部導体部の幅を前記ビ
アホール接続ランドの幅より狭くしたことを特徴とする
多層配線基板。an insulating substrate; a lower conductor portion disposed on the insulating substrate;
an insulating layer disposed on the lower conductor part and the insulating substrate with a part of the lower conductor part exposed; and a via hole connection disposed on the insulating layer above the lower conductor part. a land, and an upper conductor portion disposed on the insulating layer and connected to the via hole connection land, wherein the width of the upper conductor portion connected to the via hole connection land is narrower than the width of the via hole connection land. A multilayer wiring board characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15716488A JPH025590A (en) | 1988-06-24 | 1988-06-24 | Multilayer interconnection substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15716488A JPH025590A (en) | 1988-06-24 | 1988-06-24 | Multilayer interconnection substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH025590A true JPH025590A (en) | 1990-01-10 |
Family
ID=15643588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15716488A Pending JPH025590A (en) | 1988-06-24 | 1988-06-24 | Multilayer interconnection substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH025590A (en) |
-
1988
- 1988-06-24 JP JP15716488A patent/JPH025590A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7563645B2 (en) | Electronic package having a folded package substrate | |
| JPH025590A (en) | Multilayer interconnection substrate | |
| JPH0685425A (en) | Board for mounting electronic part thereon | |
| JPH10313170A (en) | Wiring board | |
| JP2717198B2 (en) | Method of forming bumps on printed wiring board | |
| JP2886613B2 (en) | Multilayer printed wiring board for surface mounting | |
| JPH06112395A (en) | Hybrid integrated circuit device | |
| JPH11307678A (en) | Interposer | |
| JPH03262186A (en) | Printed wiring board | |
| JP2002016330A (en) | Substrate for mounting component and its manufacturing method | |
| JPH02201945A (en) | Surface mounting type semiconductor device | |
| JPS63283051A (en) | Substrate for hybrid integrated circuit device | |
| JPH04105390A (en) | Substrate mechanism | |
| JPS61115343A (en) | Semiconductor integrated circuit | |
| JPS594061A (en) | Semiconductor device | |
| JPH06296076A (en) | Side face electrode forming method of smd module | |
| JPH02273961A (en) | Lead frame and hybrid integrated circuit using same | |
| JPH01115196A (en) | Manufacture of wiring board | |
| JPS6214959B2 (en) | ||
| JPH01181496A (en) | Connecting method of via hole | |
| JPH03185788A (en) | Formation of electric circuit | |
| JPH0595174A (en) | Flexible printed wiring board | |
| JPS61189695A (en) | Pattern structure for multi-layer printed circuit board | |
| JPH09326545A (en) | Printed wiring board mounted with surface-mount component, printed wiring board, and chip surface mount component | |
| JPH05166998A (en) | Connection method of flexible wiring board with printed circuit board by lead frame and member applied thereto |