JPH11307678A - Interposer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interposer which is capable of coping with subminiaturization of a wiring pattern keeping adhesion strength to a mounting board. SOLUTION: An interposer 30 is equipped with an interposer board 16 possessed of an IC chip joint surface 12 provided with a copper foil wiring 32 and a mounting board solder joint surface 14 provided with a copper foil wiring 20 and a conductor 22 which penetrates through the interposer board 16. In the interposer 30, the wiring 32 is thinner than a usual wiring 18 and as thick as 12 μm or so, and the wiring 20 is formed 35 μm thick as is conventionally. A solder resist film 24 is formed between the wirings 32 and 20, so as to prevent solder from flowing when a soldering operation is carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an interposer for packaging in a P-type, or an interposer for packaging small electric and electronic components, and more particularly, to miniaturization and multi-pinning of an IC chip while maintaining bonding strength with a mounting substrate, and thus wiring of the interposer. The present invention relates to an interposer that can cope with miniaturization of patterns.

[0002]

2. Description of the Related Art With the reduction in weight, size, and thickness of portable electric and electronic devices, and with the progress of digitization of electric circuits and miniaturization of electric and electronic components of electric and electronic devices,
2. Description of the Related Art Densification of wiring of a printed wiring board and mounting of packaging have been actively promoted. As the mounting density increases, IC
In the field of chip packaging, QFP (Quad Flat Pa
CSP (Chip Scale P) that has terminals (solder bumps) on the solder bonding surface of the IC package mounted on the mounting board (aka mother board) instead of the mounting board
Acknowledgment type IC packages are being widely used. CS
A P-type IC package is a package in which an IC chip is mounted on a substrate called an interposer.
The chip is mounted on a mounting board via an interposer.

Here, a configuration of a conventional interposer will be described with reference to FIG. Conventional interposer 10
As shown in FIG. 4, the solder bonding surface 12 with the mounting board, which faces the bonding surface 12 with the IC chip and the bonding surface 12 with the IC chip (hereinafter, referred to as the IC chip bonding surface 12). (Hereinafter referred to as a mounting board solder bonding surface 14). An interposer substrate 16 having wiring on both sides, and a wiring 1 on the IC chip bonding surface 12 penetrating the interposer substrate
8 to the wiring 20 on the solder joint surface 14 of the mounting board. The conductor 22 is usually formed with a through-hole penetrating the interposer substrate 16 and applying metal plating to the wall of the through-hole. The wiring 18 and the wiring 20 have the same thickness, for example, about 35
μm. In FIG. 4, some of the wires 22 are
It is cut off in the middle, but this is
8 and the wiring 20 are connected. A solder resist film 24 is formed on the IC chip bonding surface 12 between the wirings 18 and the mounting substrate solder bonding surface 14 between the wirings 20 to prevent the flow of solder when soldering.

[0004] By the way, in order to reduce the size of the CSP due to the increase in mounting density, wiring on the interposer has been increasingly finely patterned. The fine patterning of the wiring of the interposer can be realized by reducing the thickness of the wiring, for example, the thickness of the copper foil printed on the interposer substrate. However, when the copper foil is thinned, the following problems occur. That is, since the thickness of the copper foil is conventionally the same on both sides of the board, the amount of solder that enters the side face of the copper foil wiring due to the thinner copper foil at the solder joint surface with the mounting board. And the solder joint area is reduced, so that the solder joint strength with the mounting board is reduced and the reliability of mechanical and electrical joints is reduced.

On the other hand, if the thickness of the copper foil is increased to increase the solder joint strength with the mounting board to improve the reliability of mechanical and electrical joints, the wiring pattern of the interposer must be miniaturized. Can not respond to. That is, the copper foils 18 and 20
When etching to form wiring, at the top of the copper foil,
Since the progress of the etching of the copper foil is fast, the width of the copper foil becomes narrow, and the progress of the etching of the copper foil is slow at the lower part of the copper foil, so that the width of the copper foil becomes wide, and the width of the copper foil is As shown in FIG. 5, a large gap G occurs between the upper and lower portions of the copper foil.
For this reason, it is difficult to form a desired wiring by etching the copper foil according to the wiring pattern, and it is necessary to increase the distance between the wirings. For this reason, it becomes an obstacle to miniaturization of the wiring pattern, and it becomes technically difficult to finely pattern the wiring of the interposer. This is an obstacle to the high pin count and miniaturization of the CSP.

[0006]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an interposer capable of realizing a fine wiring pattern while maintaining the solder joint strength with a mounting substrate.

[0007]

In order to achieve the above object, an interposer according to the present invention uses an IC chip having a CS
An interposer for packaging in a P format, comprising: an interposer substrate having wiring on both a bonding surface with an IC chip and a solder bonding surface with a mounting substrate facing the bonding surface with the IC chip; And a conductor that penetrates through and connects the wiring at the bonding surface with the IC chip to the wiring at the solder bonding surface with the mounting board, the thickness of the wiring at the bonding surface with the IC chip is
It is characterized in that it is thinner than the thickness of the wiring on the solder joint surface with the mounting board.

The interposer of the present invention has no restrictions on the material of the wiring and the method of forming the wiring.
Wiring is formed by etching and patterning a copper foil formed on an interposer substrate. More preferably, the wiring of the interposer is patterned by etching the thin copper foil formed on one surface of the interposer substrate and the thick copper foil formed on the other surface of the interposer substrate according to the wiring pattern, respectively. It is formed by this. When etching is performed, etching conditions are determined based on a thin copper foil. The thickness of the wiring at the junction surface with the IC chip is
Although it depends on the number of pins of the chip, the shape of the wiring pattern, the wiring width, the wiring pitch, etc., it is usually 12 to 17 μm. On the other hand, the thickness of the wiring on the solder joint surface with the mounting board varies depending on the shape of the wiring pattern, the wiring width, the wiring pitch, etc., but is usually about 35 μm, which is the same as the conventional thickness, or more.

The present invention is not limited to an interposer for packaging IC chips, but can be applied as an interposer for packaging small electric / electronic components. In that case, the interposer according to the present invention includes an interposer substrate having wiring on both a bonding surface with an electric / electronic component and a solder bonding surface with a mounting substrate facing the bonding surface with the electric / electronic component. And a conductor that penetrates the interposer substrate and connects the wiring at the joint surface of the electric / electronic component to the wiring at the solder joint surface with the mounting board. It is characterized in that it is thinner than the thickness of the wiring at the solder joint surface with the mounting board.

[0010]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment Example This embodiment is an example of an embodiment of an interposer according to the present invention, and FIG. 1 is a cross-sectional view showing a configuration of the interposer of this embodiment. 1 to 3, the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 1, the interposer 30 of the present embodiment
Wiring 3 made of copper foil formed on C chip bonding surface 12
And an interposer substrate 16 having a wiring 20 made of copper foil formed on a solder joint surface 14 of the mounting substrate facing the IC chip joint surface 12;
6 to connect the wiring 32 to the wiring 20. The conductor 22 is a wiring 3 on the IC chip bonding surface 12.
2 and a wiring connecting the wiring 20 of the solder joint surface 14 of the mounting board. Usually, a through-hole penetrating the interposer substrate 16 is provided, and the wall of the through-hole is plated with metal to form a conductive wire. I have. In FIG.
Although some of the conductors 22 are cut off in the middle, they connect the wiring 32 and the wiring 20 via another path. In the present embodiment, the wiring 32 has a thickness of about 12 μm, which is thinner than the conventional wiring 18, and the wiring 20 has the same thickness of 35 μm as the conventional one.
The thickness is about m or more. A solder resist film 24 is formed between the wiring 32 and the wiring 20 to prevent the flow of solder when soldering is performed.

Next, a method of manufacturing the above-described interposer 30 will be described with reference to FIG. 2 (a) to 2 (c)
FIG. 4 is a cross-sectional view of each step when manufacturing the interposer 30. (1) First, as shown in FIG. 2A, copper is mounted on an IC chip bonding surface 12 and a mounting substrate solder bonding surface 14 of an interposer substrate 16 composed of a multilayer insulating substrate having a conductive wire 22 penetrating the substrate. The foils 32 and 20 are attached.
The thickness of the copper foil 32 is about 12 μm, and the thickness of the copper foil 20 is about 35
μm. (2) Next, as shown in FIG. 2B, a resist film is printed using a screen having a wiring pattern, and a pattern mask 34 is formed. (3) Next, using the pattern mask 34, FIG.
As shown in (1), the copper foil is chemically etched by an etchant. (4) Subsequently, if the pattern mask 34 is removed and the solder resist film 24 is formed after the removal, the interposer 30 shown in FIG. 1 can be obtained.

In the above-mentioned step (3), when etching is performed, the etchant penetrates into the copper foil portion covered with the pattern mask, and as shown in FIG. 5, the necessary copper foil portion is corroded like a valley. This often results in a gap in width between the upper and lower portions of the copper foil. This gap increases as the thickness of the copper foil increases. Therefore, in the present embodiment, a thin copper foil is used for the wiring 32, and the etching conditions are determined based on the thinner copper foil 32. This is because if the etching conditions are determined based on the thicker copper foil 20, the thinner copper foil 32 will have an undesired effect such as overetching. As a result, in the present embodiment, as shown in FIG. 3, the gap g of the upper and lower widths of the wiring 32 is much smaller than the gap G of the related art (see FIG. 5). The copper foil 32 can be etched first. In other words, the thickness of the wiring 32 on the IC chip bonding surface 12 is made thinner than the thickness of the wiring 20 on the soldering surface 14 of the mounting substrate, and the wirings 32 and 20 are patterned by etching with the thinner wiring 32 as a reference. By doing so, the wiring 32 can be etched substantially perpendicularly to the interposer substrate 16, so that the wiring 32 can be patterned according to the wiring pattern. Therefore, interposer 3
The wiring pattern of 0 can be miniaturized. On the other hand, since the wiring 20 is thick, when soldering, the solder goes around the side wall of the wiring 20 to increase the solder bonding area.
The solder bonding strength increases. Therefore, the bonding strength between the mounting board and the interposer 30 can be improved.

[0013]

According to the present invention, an IC for an interposer is provided.
By making the thickness of the wiring on the chip bonding surface thinner than the wiring thickness on the soldering surface of the mounting board, the wiring can be etched almost perpendicular to the interposer substrate when patterning the wiring. It can be patterned. Therefore, it can follow a fine wiring pattern. On the other hand, since the thickness of the wiring on the mounting board solder bonding surface is large, the bonding strength between the mounting board and the interposer can be maintained high. In addition, since a large number of patterns are drawn, the patterns can be drawn without superposing the insulating substrates to form a multilayer substrate as in the related art, so that the manufacturing cost of the interposer can be reduced. Furthermore, since the interposer according to the present invention can be manufactured in the same process as the related art, the manufacturing cost does not increase.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of an interposer according to an embodiment.

FIGS. 2A to 2C are cross-sectional views for respective steps when manufacturing the interposer of the embodiment.

FIG. 3 is a schematic diagram illustrating an effect of the interposer of the embodiment.

FIG. 4 is a cross-sectional view illustrating a configuration of a conventional interposer.

FIG. 5 is a schematic diagram illustrating a problem of a conventional interposer.

[Explanation of symbols]

10 ... conventional interposer, 12 ... IC chip bonding surface, 14 ... mounting substrate solder bonding surface, 16 ... interposer substrate, 18 ... wiring, 20 ... wiring, 22 ...
Conductor, 24 solder resist film, 30 interposer of embodiment, 32 wiring, 34 pattern mask

Claims (4)

[Claims] 1. An interposer for packaging an IC chip in a CSP format, wherein wiring is provided on both a bonding surface with the IC chip and a solder bonding surface with the mounting substrate, which is opposed to the bonding surface with the IC chip. An interposer having an interposer substrate having: and a conducting wire penetrating the interposer substrate and connecting a wiring at a bonding surface with the IC chip to a wiring at a solder bonding surface with the mounting substrate, wherein the thickness of the wiring at the bonding surface with the IC chip is Characterized in that the thickness is smaller than the thickness of the wiring at the solder joint surface with the mounting board. 2. The wiring of the interposer is patterned by etching a thin copper foil formed on one surface of the interposer substrate and a thick copper foil formed on the other surface of the interposer substrate according to a wiring pattern. The interposer according to claim 1, wherein the interposer is formed by: 3. The thickness of the wiring on the bonding surface with the IC chip is
1/3 or more of the thickness of the wiring on the solder joint surface with the mounting board 1
The interposer according to claim 1 or 2, wherein the ratio is equal to or less than / 2. 4. An interposer for a package of a small electric / electronic component, wherein both a joining surface with the electric / electronic component and a solder joining surface with the mounting substrate, which face the joining surface with the electric / electronic component. An interposer having an interposer substrate having wiring on the surface thereof, and a conductor penetrating through the interposer substrate and connecting a wiring on a bonding surface of the electric / electronic component to a wiring on a solder bonding surface with the mounting substrate. Wherein the thickness of the wiring is thinner than the thickness of the wiring at the solder joint surface with the mounting board.