JP3670466B2 - Semiconductor device package manufacturing method - Google Patents

Semiconductor device package manufacturing method Download PDF

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Publication number
JP3670466B2
JP3670466B2 JP31779197A JP31779197A JP3670466B2 JP 3670466 B2 JP3670466 B2 JP 3670466B2 JP 31779197 A JP31779197 A JP 31779197A JP 31779197 A JP31779197 A JP 31779197A JP 3670466 B2 JP3670466 B2 JP 3670466B2
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Prior art keywords
bump
forming
semiconductor device
plating
insulating layer
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JPH11145200A (en
Inventor
孝浩 永野
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Hitachi Kokusai Electric Inc
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Hitachi Kokusai Electric Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Description

【０００１】
【発明の属する技術分野】
本発明は、電子機器に用いられる薄膜集積回路等の半導体装置のパッケージ製造方法に関するものである。
【０００２】
【従来の技術】
半導体装置のパッケージ技術としては、従来は、テープキャリアパッケージ（ＴＣＰ：tape carrier package）やチップサイズパッケージ（ＣＳＰ：chip size package ）等の小型・薄型のパッケージが実用されている。以下に、一般的なＴＣＰとＣＳＰの説明をする。
【０００３】
図７は従来のテープキャリアパッケージ（ＴＣＰ）の構造を示す概要図であり、（Ａ）は部分平面図、（Ｂ）は部分縦断面図である。図において、１１は例えばポリイミドテープなどの樹脂フィルムである。この樹脂フィルム１１に多数の半導体装置が保持されている。２はバンプ、１３は封止樹脂、１４はＩＣチップ（半導体装置）、１５はインナ・リード、１６はアウタ・リードである。
このＴＣＰは、樹脂フィルム１１の上に固着された銅箔をエッチングして引出し用のインナ・リード１５のパターン形成を行い、そのインナ・リード１５と、予め半導体装置（ＩＣチップ）１４の電極部に形成されたバンプ２とをボンディング接続し、アウタ・リード１６を設け、保護の為に半導体装置を封止樹脂１３で充填保護した構造のパッケージである。
【０００４】
図８はチップサイズパッケージ（ＣＳＰ）の従来の構造断面図であり、８は配線基板、１２はその配線導体、１３は封止樹脂、１４はＩＣチップである。このＣＳＰは、予め電極としてバンプ２を形成した半導体装置（ＩＣチップ）１４を、半導体装置の電極パッドと向かい合う位置に配線導体１２が形成された配線基板８にフェースダウンボンディングで実装し、接続信頼性確保のため、半導体装置１４と配線基板８の接続部の隙間に封止樹脂１３を流し込んだ構造である。
【０００５】
【発明が解決しようとする課題】
しかし、前記従来の構成においては、例えば、ＴＣＰの場合、半導体装置１４の四方や一辺に外部接続用の電極（アウタ・リード）１６を設けるため、平面積が半導体装置１４に対してかなり大きくなってしまうという問題がある。
又、樹脂フィルム１１上にパターン形成したテープキャリアを必要とし、実装・組立てに際しては、専用の組立て装置が必要となり、材料費や製造コストが高くなり、半導体装置の製品価格が高くなってしまうという問題がある。
【０００６】
また、ＣＳＰの場合は、ＴＣＰと同様に、配線基板８を必要とし、配線導体１２の形成には高いパターン精度が要求されるため、配線基板８が高価になってしまうという問題がある。
又、製品の信頼性を確保するため、材料や組立て条件等を厳しく管理する必要があり、組立て技術が難しい等の問題もあり、製品価格が高くなっているという問題がある。
【０００７】
本発明の目的は、上記従来技術の半導体装置の小型化に対する制限と、製品のコスト高を解決し、半導体装置の大きさをベアチップサイズ程度まで小型化でき、かつ、電子携帯機器等のマザーボードへの搭載も従来の実装技術で容易に行うことができ、半導体装置の製品価格を安くすることのできる半導体装置のパッケージ製造方法を提供することにある。
【０００８】
【課題を解決するための手段】
本発明の半導体装置のパッケージの製造方法は、ウエハ状の半導体基板に多数作り込まれた集積回路の電極部分に第１のバンプを形成する第１のバンプ形成工程と、
前記第１のバンプ形成面にめっき形成可能な材料による絶縁層を形成する絶縁層形成工程と、
該絶縁層を研磨して前記第１のバンプの頭部の一部を露出させる研磨工程と、
前記第１のバンプの露出面と所定の導体配線パターンを除く他の面にめっきレジスト層を形成するめっきレジスト層形成工程と、
前記めっきレジスト層以外の面にめっきを行い前記第１のバンブに接続されためっき配線導体を形成するめっき工程と、
前記めっきレジスト層を除去するめっきレジスト除去工程と、
前記めっき配線導体上の外部回路接続用の電極部分以外にソルダーレジストを形成するソルダーレジスト形成工程と、
前記電極部分に外部端子として第２のバンプを形成する第２のバンプ形成工程と、
多数の半導体装置に分割する分割工程とを備えたことを特徴とするものである。
更に、絶縁層形成工程からめっき配線導体を形成するめっき工程までを複数回繰り返し行うことができる。
【０００９】
【発明の実施の形態】
本発明のパッケージの構成は、ウエハ状態の多数の半導体装置の電極上に形成した第１のバンプと、第１のバンプの頭部が露出するように一括処理で形成した絶縁層と、絶縁層上に第１のバンプと接続して形成した所定の配線パターンのめっき配線導体と、めっき配線導体上の電極部分に外部接続端子として形成された第２のバンプとからなっている。
【００１０】
以下、本発明の実施例の製造工程を説明する。
図１〜図４は本発明の実施例を示す製造過程の構造説明図である。これらの図において、１はウエハ状態の半導体基板、２はバンプ、３は絶縁層、４はめっきレジスト層、５はめっき配線導体である。
【００１１】
まず、第１図（Ａ）〜（Ｄ）の工程について説明する。
(1) ウエハ状態の半導体基板１を用意する。図１（Ａ）はその平面図である。この半導体基板１には多数の半導体装置が作り込まれている。
(2) ウエハ状態の半導体基板１の多数の半導体装置の電極部にバンプ（突起）２を形成する。図１（Ｂ）は斜視図であり、（Ｃ）は側面図である。
バンプ２の形成方法としては、図９（Ａ）のようなワイヤーバンピング法又は、図９（Ｂ）のようなめっきにより形成する。バンプの材質は、銅（Ｃｕ）や金（Ａｕ）等であり、電気的・機械的にめっきで接続できる材質を選定する。
(3) ウエハ状態の半導体基板１のバンプ形成面に、エポキシ樹脂やポリイミド樹脂等のめっき形成可能な材料による絶縁層３を形成する。図１（Ｄ）はその断面図である。
【００１２】
次に、図２（Ｅ）〜（Ｈ）の工程について説明する。
(4) 絶縁層３の上から、機械研磨もしくは化学研磨により、半導体基板１の電極部のバンプ２の頭部を露出させる程度に研磨する。図２（Ｅ）はその断面図、（Ｆ）はその斜視図である。
(5) バンプ２の露出面と所定の導体配線パターン以外の部分にめっきレジスト層４を形成しパターン露光を行う。図２（Ｇ）はその断面図である。
(6) その上からめっきを行いめっき配線導体５を形成する。図２（Ｈ）はその断面図であり、めっき配線導体５の一部が半導体装置の電極部のバンプ２と一体化接続されている。
【００１３】
次に、図３（Ｉ）〜（Ｋ）の工程について説明する。
(7) めっきレジスト層４を除去する。図３（Ｉ）はその断面図であり、（Ｊ）は斜視図である。
(8) めっき配線導体５上の外部端子とする電極部を除いてソルダーレジスト６を形成する。図３（Ｋ）はその断面図である。
【００１４】
(9) めっき配線導体５の外部回路接続用の電極部上に外部端子として第２のバンプ（ソルダーバンプ）７を形成する。
(10)ウエハ状態の半導体基板１を多数の半導体装置に分割する。図４（Ｌ）はその斜視図であり、本発明の半導体装置のパッケージ外観図である。
【００１５】
図５は本発明による半導体装置を配線基板８に実装する説明図であり、分割された半導体装置を配線基板８の上に従来の方法でフェースダウン実装することができる。
【００１６】
本発明のパッケージは、ベアチップ状の半導体装置の上面内に、外部との入出力端子電極（バンプ７）が形成されているので、図５のように、ベアチップの大きさでありながら、電子携帯機器等のマザーボード（配線基板）８への実装方法として、クリームハンダを
印刷してフェースダウン実装・リフローする従来の実装方法で搭載することができる。
【００１７】
図６は本発明の他の実施例の構造を示す断面図である。この他の実施例は、図３の（Ｉ）〜（Ｋ）の工程を繰り返して、絶縁層３とめっき配線導体５をそれぞれ交互に２層設けた例である。２層以上複数の層を設ける場合は、その最上面に外部回路接続端子として第２のバンプ７を設ければよい。
【００１８】
【発明の効果】
本発明を実施することにより、次のような利点がある。
（１）多数の半導体装置のパッケージの製造工程をウエハ状態で一括処理することができるため、加工コストの大幅な削減ができる。
（２）ウエハ状態の半導体基板面上に、絶縁層と外部接続用バンプを有するめっき配線導体を形成するため、一般の印刷配線板などの基板等の部材が不要になり材料コストの低減ができる。
（３）半導体基板のベアチップ面上に外部入出力端子を形成するため、パッケージの大きさをベアチップと同じ大きさにすることができる。
（４）パッケージサイズがベアチップと同等の大きさでありながら、携帯機器等のマザーボード（配線基板）へ搭載する際に特殊な実装方法を使用せずに、従来の実装技術で実装することができる。
【図面の簡単な説明】
【図１】 本発明の実施例の製造工程（Ａ）〜（Ｄ）の説明図である。
【図２】 本発明の実施例の製造工程（Ｅ）〜（Ｈ）の説明図である。
【図３】 本発明の実施例の製造工程（Ｉ）〜（Ｋ）の説明図である。
【図４】 本発明の実施例の製造工程（Ｌ）の説明図である。
【図５】 本発明のパッケージの配線基板への搭載説明図である。
【図６】 本発明の他の実施例を示す構造説明図である。
【図７】 従来のＴＣＰの構造説明図である。
【図８】 従来のＣＳＰの構造説明図である。
【図９】 バンプ形成の説明図である。
【符号の説明】
１ 半導体基板
２ バンプ
３ 絶縁層
４ めっきレジスト層
５ めっき配線導体
６ ソルダーレジスト
７ ソルダーバンプ
８ 配線基板
９ 導体パターン
１１ 樹脂フィルム
１２ 配線導体
１３ 封止樹脂
１４ ＩＣチップ
１５ インナ・リード
１６ アウタ・リード[0001]
BACKGROUND OF THE INVENTION
The present invention relates to packages Manufacturing method of semiconductor device of the thin film integrated circuit or the like used in an electronic device.
[0002]
[Prior art]
Conventionally, as a semiconductor device package technology, a small and thin package such as a tape carrier package (TCP) or a chip size package (CSP) has been put into practical use. Hereinafter, general TCP and CSP will be described.
[0003]
7A and 7B are schematic views showing the structure of a conventional tape carrier package (TCP), where FIG. 7A is a partial plan view and FIG. 7B is a partial vertical sectional view. In the figure, 11 is a resin film such as a polyimide tape. A number of semiconductor devices are held on the resin film 11. 2 is a bump, 13 is a sealing resin, 14 is an IC chip (semiconductor device), 15 is an inner lead, and 16 is an outer lead.
In this TCP, the copper foil fixed on the resin film 11 is etched to form a pattern of the inner lead 15 for extraction, and the inner lead 15 and the electrode portion of the semiconductor device (IC chip) 14 in advance are formed. This is a package having a structure in which the bumps 2 formed by bonding are connected by bonding, outer leads 16 are provided, and the semiconductor device is filled and protected with a sealing resin 13 for protection.
[0004]
FIG. 8 is a sectional view of a conventional structure of a chip size package (CSP), in which 8 is a wiring board, 12 is a wiring conductor thereof, 13 is a sealing resin, and 14 is an IC chip. In this CSP, a semiconductor device (IC chip) 14 in which bumps 2 are formed in advance as electrodes is mounted by face-down bonding on a wiring board 8 on which a wiring conductor 12 is formed at a position facing an electrode pad of the semiconductor device. The sealing resin 13 is poured into the gap between the connection portion of the semiconductor device 14 and the wiring board 8 to ensure the reliability.
[0005]
[Problems to be solved by the invention]
However, in the conventional configuration, for example, in the case of TCP, since the electrodes (outer leads) 16 for external connection are provided on the four sides and one side of the semiconductor device 14, the plane area is considerably larger than that of the semiconductor device 14. There is a problem that it ends up.
In addition, a tape carrier patterned on the resin film 11 is required, and a dedicated assembling apparatus is required for mounting and assembling, resulting in high material costs and manufacturing costs, and high product prices for semiconductor devices. There's a problem.
[0006]
In the case of CSP, similarly to TCP, the wiring board 8 is required, and the formation of the wiring conductor 12 requires high pattern accuracy, so that there is a problem that the wiring board 8 becomes expensive.
In addition, in order to ensure the reliability of the product, it is necessary to strictly manage materials and assembly conditions, and there are problems such as difficulty in assembly technology, and there is a problem that the product price is high.
[0007]
The object of the present invention is to solve the above-described limitations on the miniaturization of the semiconductor device and the high cost of the product, to reduce the size of the semiconductor device to the bare chip size, and to a motherboard such as an electronic portable device. mounting can also be easily performed by conventional mounting technique is to provide a package Manufacturing method of a semiconductor device capable of cheaper product prices of the semiconductor device.
[000 8 ]
[Means for Solving the Problems]
The semiconductor device package manufacturing method of the present invention includes a first bump forming step of forming first bumps on electrode portions of an integrated circuit formed in a large number on a wafer-like semiconductor substrate;
An insulating layer forming step of forming an insulating layer made of a material capable of being plated on the first bump forming surface;
A polishing step of polishing the insulating layer to expose a part of the head of the first bump;
A plating resist layer forming step of forming a plating resist layer on the other surface excluding the exposed surface of the first bump and the predetermined conductor wiring pattern;
Plating to form a plated wiring conductor connected to the first bump by plating on a surface other than the plating resist layer;
A plating resist removing step for removing the plating resist layer;
A solder resist forming step of forming a solder resist other than the electrode part for connecting an external circuit on the plated wiring conductor;
A second bump forming step of forming a second bump as an external terminal on the electrode portion;
And a dividing step of dividing the semiconductor device into a large number of semiconductor devices.
Furthermore, the process from the insulating layer forming process to the plating process for forming the plated wiring conductor can be repeated a plurality of times.
[000 9 ]
DETAILED DESCRIPTION OF THE INVENTION
The structure of the package of the present invention includes a first bump formed on electrodes of a number of semiconductor devices in a wafer state, an insulating layer formed by batch processing so that the heads of the first bump are exposed, and an insulating layer It consists of a plated wiring conductor having a predetermined wiring pattern formed on and connected to the first bump, and a second bump formed as an external connection terminal on the electrode portion on the plated wiring conductor.
[00 10 ]
Hereafter, the manufacturing process of the Example of this invention is demonstrated.
1 to 4 are explanatory views of the structure of the manufacturing process showing an embodiment of the present invention. In these drawings, 1 is a semiconductor substrate in a wafer state, 2 is a bump, 3 is an insulating layer, 4 is a plating resist layer, and 5 is a plated wiring conductor.
[00 11 ]
First, the steps of FIGS. 1A to 1D will be described.
(1) A semiconductor substrate 1 in a wafer state is prepared. FIG. 1A is a plan view thereof. A large number of semiconductor devices are built in the semiconductor substrate 1.
(2) Bumps (projections) 2 are formed on the electrode portions of a number of semiconductor devices on the semiconductor substrate 1 in the wafer state. FIG. 1B is a perspective view, and FIG. 1C is a side view.
The bump 2 is formed by a wire bumping method as shown in FIG. 9A or plating as shown in FIG. 9B. The material of the bump is copper (Cu), gold (Au) or the like, and a material that can be electrically and mechanically connected by plating is selected.
(3) The insulating layer 3 is formed on the bump forming surface of the semiconductor substrate 1 in the wafer state using a material capable of plating such as epoxy resin or polyimide resin. FIG. 1D is a cross-sectional view thereof.
[00 12 ]
Next, the steps of FIGS. 2E to 2H will be described.
(4) Polishing from above the insulating layer 3 by mechanical polishing or chemical polishing to the extent that the heads of the bumps 2 of the electrode portions of the semiconductor substrate 1 are exposed. FIG. 2E is a cross-sectional view thereof, and FIG.
(5) A plating resist layer 4 is formed on portions other than the exposed surface of the bump 2 and a predetermined conductor wiring pattern, and pattern exposure is performed. FIG. 2G is a cross-sectional view thereof.
(6) The plated wiring conductor 5 is formed by plating from above. FIG. 2H is a cross-sectional view thereof, in which a part of the plated wiring conductor 5 is integrally connected to the bump 2 of the electrode portion of the semiconductor device.
[00 13 ]
Next, the steps of FIGS. 3I to 3K will be described.
(7) The plating resist layer 4 is removed. FIG. 3I is a sectional view thereof, and FIG. 3J is a perspective view thereof.
(8) A solder resist 6 is formed except for the electrode portion serving as an external terminal on the plated wiring conductor 5. FIG. 3K is a cross-sectional view thereof.
[00 14 ]
(9) A second bump (solder bump) 7 is formed as an external terminal on the electrode portion for connecting an external circuit of the plated wiring conductor 5.
(10) The semiconductor substrate 1 in a wafer state is divided into a large number of semiconductor devices. FIG. 4L is a perspective view of the package of the semiconductor device of the present invention.
[00 15 ]
FIG. 5 is an explanatory diagram for mounting the semiconductor device according to the present invention on the wiring board 8, and the divided semiconductor device can be face-down mounted on the wiring board 8 by a conventional method.
[00 16 ]
In the package of the present invention, since input / output terminal electrodes (bumps 7) to the outside are formed in the upper surface of the bare chip-shaped semiconductor device, the size of the bare chip as shown in FIG. As a mounting method on a mother board (wiring board) 8 such as a device, it can be mounted by a conventional mounting method in which cream solder is printed and face-down mounted and reflowed.
[00 17 ]
FIG. 6 is a sectional view showing the structure of another embodiment of the present invention. In another example, the steps (I) to (K) in FIG. 3 are repeated to provide two insulating layers 3 and two plated wiring conductors 5 alternately. When two or more layers are provided, the second bumps 7 may be provided on the uppermost surface as external circuit connection terminals.
[00 18 ]
【The invention's effect】
By implementing the present invention, there are the following advantages.
(1) Since the manufacturing process of a large number of semiconductor device packages can be collectively processed in a wafer state, the processing cost can be greatly reduced.
(2) Since the plated wiring conductor having the insulating layer and the bumps for external connection is formed on the semiconductor substrate surface in the wafer state, a member such as a general printed wiring board is not necessary, and the material cost can be reduced. .
(3) Since the external input / output terminals are formed on the bare chip surface of the semiconductor substrate, the size of the package can be made the same as that of the bare chip.
(4) Although the package size is the same as that of a bare chip, it can be mounted by conventional mounting technology without using a special mounting method when mounting on a mother board (wiring board) of a portable device or the like. .
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of manufacturing steps (A) to (D) according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of manufacturing steps (E) to (H) according to an embodiment of the present invention.
FIG. 3 is an explanatory diagram of manufacturing steps (I) to (K) according to an embodiment of the present invention.
FIG. 4 is an explanatory diagram of a manufacturing process (L) according to an embodiment of the present invention.
FIG. 5 is an explanatory diagram of mounting the package of the present invention on a wiring board;
FIG. 6 is a structural explanatory view showing another embodiment of the present invention.
FIG. 7 is a diagram illustrating the structure of a conventional TCP.
FIG. 8 is a diagram illustrating the structure of a conventional CSP.
FIG. 9 is an explanatory diagram of bump formation.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Bump 3 Insulating layer 4 Plating resist layer 5 Plating wiring conductor 6 Solder resist 7 Solder bump 8 Wiring board 9 Conductive pattern 11 Resin film 12 Wiring conductor 13 Sealing resin 14 IC chip 15 Inner lead 16 Outer lead

Claims (2)

ウエハ状の半導体基板に多数作り込まれた集積回路の電極部分に第１のバンプを形成する第１のバンプ形成工程と、
前記第１のバンプ形成面にめっき形成可能な材料による絶縁層を形成する絶縁層形成工程と、
該絶縁層を研磨して前記第１のバンプの頭部の一部を露出させる研磨工程と、
前記第１のバンプの露出面と所定の導体配線パターンを除く他の面にめっきレジスト層を形成するめっきレジスト層形成工程と、
前記めっきレジスト層以外の面にめっきを行い前記第１のバンブに接続されためっき配線導体を形成するめっき工程と、
前記めっきレジスト層を除去するめっきレジスト除去工程と、
前記めっき配線導体上の外部回路接続用の電極部分以外にソルダーレジストを形成するソルダーレジスト形成工程と、
前記電極部分に外部端子として第２のバンプを形成する第２のバンプ形成工程と、
多数の半導体装置に分割する分割工程と
を備えた半導体装置のパッケージ製造方法。A first bump forming step of forming first bumps on electrode portions of an integrated circuit formed in a large number on a wafer-like semiconductor substrate;
An insulating layer forming step of forming an insulating layer made of a material that can be plated on the first bump forming surface;
A polishing step of polishing the insulating layer to expose a part of the head of the first bump;
A plating resist layer forming step of forming a plating resist layer on the other surface excluding the exposed surface of the first bump and the predetermined conductor wiring pattern;
A plating step of plating a surface other than the plating resist layer to form a plated wiring conductor connected to the first bump;
A plating resist removing step for removing the plating resist layer;
A solder resist forming step of forming a solder resist other than the electrode part for connecting an external circuit on the plated wiring conductor;
A second bump forming step of forming a second bump as an external terminal on the electrode portion;
A semiconductor device package manufacturing method comprising: a dividing step of dividing the semiconductor device into a plurality of semiconductor devices. 請求項３記載の絶縁層形成工程からめっき配線導体を形成するめっき工程までを複数回繰り返し行うことを特徴とする請求項１記載の半導体装置のパッケージ製造方法。4. The semiconductor device package manufacturing method according to claim 1 , wherein the process from the insulating layer forming step to the plating step for forming the plated wiring conductor is repeated a plurality of times.
JP31779197A 1997-11-05 1997-11-05 Semiconductor device package manufacturing method Expired - Fee Related JP3670466B2 (en)

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JP2001007529A (en) * 1999-06-23 2001-01-12 Ibiden Co Ltd Multilayer printed wiring board and its manufacture, and semiconductor chip and its manufacture

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