JPH01181496A - Connecting method of via hole - Google Patents
Connecting method of via holeInfo
- Publication number
- JPH01181496A JPH01181496A JP290088A JP290088A JPH01181496A JP H01181496 A JPH01181496 A JP H01181496A JP 290088 A JP290088 A JP 290088A JP 290088 A JP290088 A JP 290088A JP H01181496 A JPH01181496 A JP H01181496A
- Authority
- JP
- Japan
- Prior art keywords
- via hole
- layer conductor
- outer layer
- solder
- fan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 10
- 239000004020 conductor Substances 0.000 claims abstract description 44
- 229910000679 solder Inorganic materials 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 15
- 238000001816 cooling Methods 0.000 abstract description 3
- 230000004907 flux Effects 0.000 abstract description 3
- 230000005496 eutectics Effects 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 229910020816 Sn Pb Inorganic materials 0.000 abstract 1
- 229910020922 Sn-Pb Inorganic materials 0.000 abstract 1
- 229910008783 Sn—Pb Inorganic materials 0.000 abstract 1
- 238000007598 dipping method Methods 0.000 abstract 1
- 239000004593 Epoxy Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ビデオテープレコーダー、テレビジョン受像
機などの各種電子機器や装置に用いる多層配線基板のビ
アホールの接続方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for connecting via holes in multilayer wiring boards used in various electronic devices and devices such as video tape recorders and television receivers.
従来の技術
従来のセラミックや樹脂を絶縁基材とする多層基板は第
３図で示すように、アルミナやガラスエポキシなどの絶
縁基材２１の上に第一層目の導体２がＡｇ−ＰｄやＣｕ
などでそれぞれ形成され、さらに上記と同一絶縁材料と
同一導体材料を用いて第二層目の絶縁層３と導体層２４
とがそれぞれ形成され、多層化構成されるものである。BACKGROUND OF THE INVENTION A conventional multilayer board using ceramic or resin as an insulating base material has a first layer conductor 2 on an insulating base material 21 of alumina, glass epoxy, etc. Cu
A second insulating layer 3 and a second conductive layer 24 are formed using the same insulating material and the same conductive material as above.
are formed respectively, resulting in a multilayer structure.
一般的にこれらの多層基板３ｏば、第１層目の導体（内
層導体）２２と第２層目の導体（外層導体）２４とを電
気的に接続するだめのビアホール２５を有している。内
層導体２２と外層導体２４とをビアホール２５を通じて
電気的に接続し、多層配線基板として機能させる方法と
しては多層導体２４の形成時と一緒に同一材料を用いて
一体的に形成する場合もあるが、多層基板３ｏの形成後
、別の手段、たとえば半田材を用いて部品実装時に導通
短絡することもたびたび用いられる発明が解決しようと
する課題
このような従来の多層基板３ｏに対してビアホール２６
内に５ｎ−ｐｂに代表されるような半田材２６を供給レ
リフローやデイツプなどの手段を用いて、内層導体２２
と外層導体２４とを半田接合し短絡しようとすると、加
熱時のビアホール界面および外層導体部近傍における溶
融半田の表面張力バランスが比較的均衡していることか
ら半田がビアホール上を塞いでしまい、その結果、内部
にフラックスなどから発生するガスが滞留することとな
り、冷却した後は第４図に示すようなビアホール２６の
中に気泡２７を内在させてしまう状態となる。その結果
内層導体２２と外層導体２４とは接続不安定となり、信
頼性の確保が困難になるという問題点を有していた。Generally, these multilayer substrates 3o have via holes 25 for electrically connecting the first layer conductor (inner layer conductor) 22 and the second layer conductor (outer layer conductor) 24. As a method of electrically connecting the inner layer conductor 22 and the outer layer conductor 24 through the via hole 25 to function as a multilayer wiring board, there are cases where the inner layer conductor 22 and the outer layer conductor 24 are integrally formed using the same material when forming the multilayer conductor 24. After forming the multilayer board 3o, conductive short circuits are often caused during component mounting using another means, such as a solder material.The problem to be solved by the present invention is that the via hole 26 is
The inner layer conductor 22 is supplied with a solder material 26 such as 5n-pb inside the inner layer conductor 22 using a method such as reflow or dip.
If an attempt is made to solder and short-circuit the outer layer conductor 24 and the outer layer conductor 24, the surface tension of the molten solder at the via hole interface and near the outer layer conductor portion during heating is relatively balanced, so the solder will block the top of the via hole. As a result, gas generated from flux or the like will remain inside, and after cooling, air bubbles 27 will be contained within the via holes 26 as shown in FIG. As a result, the connection between the inner layer conductor 22 and the outer layer conductor 24 becomes unstable, resulting in a problem that it becomes difficult to ensure reliability.
本発明は上記課題に鑑み、ビアホールに内在する気泡を
取り除き上下導体を接合短絡し信頼性のあるビアホール
の接続方法を提供するものである。In view of the above-mentioned problems, the present invention provides a reliable method for connecting via holes by removing air bubbles present in the via holes and joining and short-circuiting upper and lower conductors.
課題を解決するだめの手段
本発明はかかる課題を解決するためビアホールをとり囲
む円形状の外層導体の一部に扇形の欠落部を形成しビア
ホールを介して、半田材によって内層導体と接合短絡す
るものである。Means to Solve the Problem In order to solve the problem, the present invention forms a fan-shaped missing part in a part of the circular outer layer conductor surrounding the via hole, and connects and short-circuits it with the inner layer conductor using a solder material through the via hole. It is something.
作用
本発明は上記の方法により、供給充填された溶融半田の
表面張力バランスの不均衡化を図ることによってビアホ
ール内の気泡滞留を防止し、内外層の接続安定化を図る
ものである。Function The present invention uses the method described above to unbalance the surface tension of the supplied molten solder, thereby preventing air bubbles from remaining in the via hole and stabilizing the connection between the inner and outer layers.
実施例
以下本発明の一実施例のビアホールの接続方法について
、図面を参照しながら説明する。EXAMPLE Hereinafter, a method for connecting via holes according to an example of the present invention will be described with reference to the drawings.
第１図〜第２図は本発明のビアホールの接続方法とビア
ホール接続部の断面状態を示すものである。１はアルミ
ナやガラスエポキシなどからなる絶縁基材であり、その
上に内層導体２がＡｇ−ＰｄやＣｕなどで形成されてい
る。さらに上記とＭ −の絶縁材料と導体材料を用いて
それぞれ絶縁層３と外層導体４とが形成される。内層導
体２と外層導体４との接続のためにビアホール６が配設
されており、その周囲をとり囲んでいる円形状の外層導
体接続部４ａの一部に扇形の欠落部８が設けられ、多層
（２層）基板となる。内層導体２と外層導体４とを接続
するためにビアホール５内に、例えば５ｎ−Ｐｂ共晶半
田を供給充填し、リフローやデイツプなどの手段を用い
て上記半田材を加熱溶融する。この時、溶融した半田材
６がビアホール６上を覆うこととなるが、ビアホールＳ
の周囲をとり囲んでいる円形状の外層導体接続部４ａの
一部に予め扇形欠落部８が設けられていることから、溶
融半田の表面張力バランスが崩れ、ビアホール５内に滞
留しているフラックスからのガスが扇形欠落部８を通じ
て排出されることとなシ、冷却後は第２図に示すように
、ビアホールＳ内に気泡発生のない半田材６を用いた内
層導体２と外層導体４との接続状態が得られることとな
る。その結果、接続の安定化が図られ、したがって、高
信頼性を確保できるものである。1 and 2 show the via hole connecting method of the present invention and the cross-sectional state of the via hole connecting portion. Reference numeral 1 denotes an insulating base material made of alumina, glass epoxy, or the like, on which an inner layer conductor 2 is formed of Ag-Pd, Cu, or the like. Further, an insulating layer 3 and an outer layer conductor 4 are formed using the above-mentioned and M- insulating materials and conductive materials, respectively. A via hole 6 is provided for connection between the inner layer conductor 2 and the outer layer conductor 4, and a fan-shaped missing portion 8 is provided in a part of the circular outer layer conductor connection portion 4a surrounding the via hole 6. It becomes a multilayer (two-layer) board. In order to connect the inner layer conductor 2 and the outer layer conductor 4, for example, 5n-Pb eutectic solder is supplied and filled into the via hole 5, and the solder material is heated and melted using means such as reflow or dip. At this time, the melted solder material 6 will cover the via hole 6, but the via hole S
Since the sector-shaped cutout part 8 is provided in advance in a part of the circular outer layer conductor connection part 4a surrounding the periphery, the surface tension balance of the molten solder is disrupted, and the flux staying in the via hole 5. After cooling, as shown in FIG. The connection status will be obtained. As a result, the connection is stabilized, and therefore high reliability can be ensured.
発明の効果
以上のように本発明はビアホールの周囲の円形状の外層
導体の一部に扇形の欠落部を設けることにより、非常に
簡単な多層基板構成を用いて、安定なビアホールの接続
状態が得られることから、工業上極めて有益な発明とな
るものである。Effects of the Invention As described above, the present invention provides a sector-shaped cutout in a part of the circular outer layer conductor around the via hole, thereby achieving a stable via hole connection state using a very simple multilayer board configuration. Therefore, it is an industrially extremely useful invention.
第１図は本発明の一実施例におけるビアホールの接続方
法を説明するための多層配線基板の断面斜視図、第２図
は同要部断面図、第３図は従来のビアホールの接続方法
を説明するだめの多層配線基板の断面斜視図、第４図は
同要部断面図である。
１・・・・・・絶縁基材、２ ・・・第１全溝体（内層
導体）、３・・・・・絶縁層、４・・・・・・第２全溝
本（外層導体）、４ａ・・・・・・外層導体接続部、５
・・・・・・ビアホール、６・・・・・・半田材、７・
・・・・・気泡、８・・・・・・扇形欠落部、１Ｑ、１
１・・・・・・多層基板。FIG. 1 is a cross-sectional perspective view of a multilayer wiring board for explaining a method for connecting via holes in an embodiment of the present invention, FIG. 2 is a cross-sectional view of the same essential parts, and FIG. 3 is for explaining a conventional method for connecting via holes. FIG. 4 is a cross-sectional perspective view of the multilayer wiring board, and FIG. 4 is a cross-sectional view of the main parts thereof. 1... Insulating base material, 2... First full groove body (inner layer conductor), 3... Insulating layer, 4... Second full groove body (outer layer conductor) , 4a...Outer layer conductor connection part, 5
...... Via hole, 6... Solder material, 7.
...Bubble, 8...Sector-shaped missing part, 1Q, 1
1...Multilayer board.
Claims (1)
部に扇形の欠落部を形成し、ビアホール内に半田材を充
填することによって内層導体と上記外層導体とを接合短
絡するビアホールの接続方法。A via hole connection method in which a circular outer layer conductor is placed around the via hole, a fan-shaped cutout is formed in a part of the outer layer conductor, and the inner layer conductor and the outer layer conductor are bonded and short-circuited by filling the via hole with solder material. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP290088A JPH01181496A (en) | 1988-01-08 | 1988-01-08 | Connecting method of via hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP290088A JPH01181496A (en) | 1988-01-08 | 1988-01-08 | Connecting method of via hole |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01181496A true JPH01181496A (en) | 1989-07-19 |
Family
ID=11542228
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP290088A Pending JPH01181496A (en) | 1988-01-08 | 1988-01-08 | Connecting method of via hole |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01181496A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5657830A (en) * | 1990-08-02 | 1997-08-19 | Honda Giken Kogyo Kabushini Kaisha | Electrically operated saddle type vehicle |
-
1988
- 1988-01-08 JP JP290088A patent/JPH01181496A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5657830A (en) * | 1990-08-02 | 1997-08-19 | Honda Giken Kogyo Kabushini Kaisha | Electrically operated saddle type vehicle |
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