JPH0251745A - History data control system - Google Patents

Abstract

PURPOSE:To improve the efficiency of a debugging job, etc., by holding the control storage read addresses of a micro processor by an amount equal to the stage number of a pipeline when the read address of a control storage is stored in a history memory. CONSTITUTION:A read address register RCC for read address given from a control storage CS, a control storage address register RCD for decoding cycle of a microinstruction, and a control storage address register RCE for executing cycle are added to a microprocessor containing the CS and a history memory HM. When the read address of the CS is stored in the memory HM, the CS read addresses of the microprocessor are held until an executing cycle by an amount equal to the stage number of a pipeline. Then the CS read addresses are held continuously in response to the executing cycle when this cycle is extended. Then the CS read addresses are written into the HM.

Description

[Detailed Description of the Invention] [Summary] In a microprocessor having a history memory,
Regarding the history data control method when storing the read address of the control memory in the history memory, data that is not directly related to the actual microprocessor operation is not stored in the history memory, and the work of decoding the history memory is facilitated. In a microprocessor having a control memory and a history memory, the purpose of which is to improve the efficiency of debugging work, etc., a read address register from the control memory, a control memory address register for the decode cycle of micro instructions, and a control memory address register for the execution cycle. and a storage address register, and when storing the read address of the control memory in the history memory, the control memory read address of the microprocessor is held for the number of pipeline stages until an execution cycle is reached, and the execution cycle is When extended, the control memory read address corresponding to the execution cycle is continued to be held based on the clock signal, and the control memory read address is written to the history memory.

[Industrial application field]

The present invention relates to a history data control method for controlling data transfer from a control memory read address register to the history memory when a control memory read address is stored in the history memory in a microprocessor having a history memory.

In recent years, an increasing number of microprocessors are equipped with history memory in order to improve the efficiency of debugging work and the like. In microprocessors, read addresses of control memory are often stored in history memory. Therefore, since the memory has a limited capacity, it is preferable that the data stored in the history memory be as simple and clear as possible without including any unnecessary information. It is necessary to improve efficiency.

Note that the history memory is a memory that overwrites information in the information processing device every predetermined cycle to store a history of the change process.

[Prior art and problems to be solved by the invention] Fig. 4 is a block diagram of a conventional microprocessor, which has a three-stage pipeline consisting of stages C, D, and E. FIG. In the figure, the C stage is a stage for reading control memory, the D stage is a stage for checking ECC codes for error checking and correction, and microinstruction decoding, and the E stage is a stage for executing microinstructions. . Note that C8 is a control memory, RCC is a register that stores read addresses C5A-C from the control memory, C3A is a control unit that increments and branches addresses C8^-〇, and RMD is a microcode read from the control memory C8. Microinstruction M in D cycle (D stage) of
A register that stores OP-D, RME a register that stores microinstruction MOP-8 of the E cycle (E stage) of the microcode read from the control memory C8, and RHD a register that stores data stored in the history memory)l-1)
register that stores ata, HM is history memory, R
HA is a register that stores the history memory write address HA, and RC is an execution control unit. Note 1. MOP-C
is a C cycle microinstruction.

5(a) to 5(d) are time charts of the configuration shown in FIG. 4. (a) is a normal instruction, (b) is a branch instruction, (C) is when instruction B is a 2τ instruction, (d) is C
Indicates when there is a 3I bit error. A-E are each instruction.

In case (a), if each instruction is 1τ, the C-D-E cycle and pipeline processing are performed sequentially as is, and the necessary data is stored in the register RHD at each address of each instruction, so there is no problem. do not have.

In the branch instruction in (b), 1 of the E stage (MOP-8)
Since the next address is determined in the cycle, branch instruction B becomes a 3τ instruction in the execution cycle, but register RCC contains the other two instructions 3+l and [l at the address next to the branch instruction.
+2 is input. B+1. B+2 is the address of an unexecuted instruction that is not needed during the execution of branch instruction B,
This was stored as history data in the history memo 'JHM. Note that T is a target instruction.

If instruction B in (C) is a 2r instruction, B at the E stage
At the time of execution, the address after two instructions is manually entered in the register RCC, so MOP-C is taken in as is and the instruction number 2τ is stored.

If instruction A in (d) has a C3I bit error, instruction A is 1
The error detection circuit ECC detects that a pit error has occurred, and the error determination is performed at the E stage. By the time the determination is made, the following two instructions are manually input to the C stage and D stage, and further error correction is performed. Re-execute A from stage C. Therefore, B and C, which are not executed, are stored as history data.

In this way, in the past, data not directly related to actual microprocessor operations was stored in the history memory, which often made it difficult to decipher the history memory.

SUMMARY OF THE INVENTION An object of the present invention is to prevent data not directly related to actual microprocessor operations from being stored in the history memory, thereby facilitating the decoding of the history memory and improving the efficiency of debugging and the like.

[Means and effects for solving the problems] FIG. 1 is a diagram showing the basic configuration of the present invention. As shown in the figure, in a microprocessor having a control memory (CS) and a history memory (HM), a read address register (RCC) from the control memory and a control memory for decoding cycles of microinstructions are provided. Address register (RC
D) and the execution cycle control storage address register (R
CE), when storing the read address of the control memory in the history memory, the read address of the control memory of the microprocessor is held until the execution cycle is extended by the number of stages of the pipeline, and the execution cycle is extended. When the execution cycle is executed, the control memory read address corresponding to the execution cycle is continued to be held based on the clock signal, and the control memory read address is written to the history memory.

〔Example〕

FIG. 2 is a block diagram of a microprocessor according to an embodiment of the present invention. As shown in the figure, this configuration is a microprocessor having a three-stage pipeline consisting of three stages each of C, D, and E, similar to the conventional microprocessor. Therefore, the common configuration with the conventional one is the same as described above: the C stage is a stage for reading control memory, the D stage is a stage for checking ECC codes and microinstruction decoding for error checking and correction, and the E stage is a stage for performing microinstruction decoding. This is the stage where microinstructions are executed. Note that C8 is a control memory, RCC is a read address register from the control memory, C3A is a control unit that increments and branches read addresses C5A-C, and RMD is a D cycle microinstruction of the microcode read from the control unit +1CS. The register storing MOP-D, RME is also the microinstruction MO of the E cycle of the microcode read from the control memory C8.
A register that stores P-8, HM is a history memory,
RHA is a register that stores the history memory write address HA, and RC is an execution control unit. There is no longer a register RHD that stores data to be stored in the history memory HM, but a register RCD that stores the control memory read addresses C5A-D corresponding to the D stage and a control memory read address C8^-8 that corresponds to the E stage. By providing a register RCE for storing the control memory address of the execution cycle and writing the control memory address of the execution cycle for history instead of conventionally writing the control memory address C5A-C of the C cycle to the history memory, the address being executed can only be written to history memory.

FIGS. 4(a) to 4(d) are time charts of the configuration shown in FIG. (a) is a normal instruction, (b) is a branch instruction, (C) is when instruction B is a 2τ instruction, (d) is C
Indicates when there is a 3I pit error. A-E are each instruction.

In the present invention, by providing the above two registers RCD and RCE and performing appropriate lock control, only executed instructions are stored in the correct number of cycles as described below. That is, appropriate timing for entering the D cycle and E cycle is given to each control storage address CS^-0, C3A- under the control of the clock signal CLK.

In case (a), if each instruction is 1τ, pipeline processing is performed sequentially as is, and register RMD is transferred to register RCD and register RME is transferred to register RCE under clock control, so there is no problem. .

In the branch instruction (b), the contents of register RMD are transferred to register RCD under clock control, and the contents of register RMD are transferred to register RCD.
Since the contents of ME are transferred to register RCE, B+1.8+2, which is the address of the unexecuted instruction, is not stored in the history memory HM as history data as in the conventional case.

When instruction B in (C) is a 2τ instruction, the contents of register RMD are transferred to register RCD under clock control, and the contents of register RME are transferred to register RCE, so the contents of register RCE are stored, and the conventional Thus, the address D after two instructions will not be stored in 2r.

If instruction A in (d) has a C8I bit error, the error determination is made at the E stage, but while the determination is being made, 8 is input to the register RCE, so 8 is continuously stored in the history memory, and the error is determined in the E stage. B and C, which are not executed, will not be stored as history data.

〔Effect of the invention〕

As explained above, according to the present invention, the data stored in the history memory is all related to execution cycles, so there is no need for extra translation work when decoding the history memory, which improves the efficiency of debugging work, etc. It is effective above.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention; FIG. 2 is a block diagram of a microprocessor according to an embodiment of the present invention; FIGS. 3(a) to 3(d) are time charts of the configuration in FIG. 2; FIG. 4 is a block diagram of a conventional microprocessor, and FIGS. 5(a) to 5(d) are time charts of the configuration shown in FIG. (Explanation of symbols) C8...Control memory, C3A...Control memory address control unit, HM...History memory, RC...Execution control unit, RMD, RME, RCC, RCD, RCE. RD, RHA...Register. Principle configuration diagram of the present invention 1st FA An embodiment of the present invention Micropro seven nose beak diagram $2 times ECC゛ ・Error detection capital MOP-C A B C D E MOP-D A C D E MOP-E A B C D E CSA-E A B C D E (a) MOP-E B B B ■ T Ya 1 Figure 2 Configuration time chart (Part 1) Figure Kei Conventional Microgrossenosa configuration diagram Figure HM ...History memory RC...Execution control unit MOP-C A B C D D E MOP-E A B B C D E (C) MOP-E A B C A B C CS+ Bit effect E-effective configuration shown in Figure 2 Time chart (Part 2) MOP-C A B C D E MOP-E A B C D E H-Data A B C D E MOP-E B B B ■ T+1 H-Data B B・1 Bφ2 T T・1 (b) MOP-E A B B C D E H-Data A C D D E (C) Time chart of Figure 4 configuration]・(Part 1) Figure

Claims (1)

[Claims] 1. In a microprocessor having a control memory (CS) and a history memory (HM), a read address register (RCC) from the control memory;
and a control memory address register (RCD) for a microinstruction decode cycle, and a control memory address register (RCE) for an execution cycle, and when storing the read address of the control memory in the history memory, the microprocessor The control memory read address is held for the number of pipeline stages until the execution cycle is reached, and when the execution cycle is extended, the control memory read address corresponding to the execution cycle is continued to be held based on the clock signal. A history data control method, characterized in that the control storage read address is written into a history memory.