JPH025023B2 - - Google Patents
Info
- Publication number
- JPH025023B2 JPH025023B2 JP58090931A JP9093183A JPH025023B2 JP H025023 B2 JPH025023 B2 JP H025023B2 JP 58090931 A JP58090931 A JP 58090931A JP 9093183 A JP9093183 A JP 9093183A JP H025023 B2 JPH025023 B2 JP H025023B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- layer
- insulating layer
- opening
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 description 3
Description
【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は厚膜多層配線基板に関する。[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a thick film multilayer wiring board.
従来、厚膜多層配線基板は、セラミツク基板に
導電性ペースト及び絶縁性ペーストを用いて多層
構成としている。導電性ペーストを用いて下側導
体層を形成し、次に絶縁性ペーストを用いて下側
絶縁層を形成し、この下側絶縁層上に中間導体層
を形成し、更にその上に上側絶縁層を形成すると
いう工程を繰返して多層化しようとするとき、下
側導体層と中間導体層を接続するために下側絶縁
層に予め開口を設け、導電性ペーストをこの開口
に入れて接続を図るというように構成されていた
ので、この接続用開口上にくる上側絶縁層にはピ
ンホールが生じ易く、接続用開口の上部に上側絶
縁層を挾んで形成される上側導体層との間で時折
電気的短絡を起こすという欠点があつた。
Conventionally, thick film multilayer wiring boards have a multilayer structure using conductive paste and insulating paste on a ceramic substrate. A lower conductor layer is formed using a conductive paste, a lower insulating layer is formed using an insulating paste, an intermediate conductor layer is formed on the lower insulating layer, and an upper insulating layer is further formed on top of the lower insulating layer. When attempting to create a multilayer structure by repeating the process of forming layers, an opening is created in advance in the lower insulating layer to connect the lower conductor layer and the intermediate conductor layer, and conductive paste is inserted into this opening to make the connection. Since the upper insulating layer above the connection opening is easily formed with pinholes, pinholes are likely to form between the upper conductor layer formed above the connection opening and sandwiching the upper insulating layer. The drawback was that it occasionally caused electrical short circuits.
本発明の目的は、上記欠点を除去し、上側導体
層と下側もしくは中間導体層との短絡をなくした
厚膜多層配線基板を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a thick film multilayer wiring board that eliminates the above drawbacks and eliminates short circuits between the upper conductor layer and the lower or intermediate conductor layer.
本発明は、絶縁体層上もしくは少くとも表面が
絶縁体である基板上に設けられた下側導体層と、
少くとも該下側導体層を覆うように形成された下
側絶縁層と、前記下側導体層上に位置するように
前記下側絶縁層に設けられた接続用の開口部と、
前記下側絶縁層の上に設けられかつ前記開口部を
通して前記下側導体層と接続する中間導体層と、
少くとも該中間絶縁層を覆うように設けられた上
側絶縁層と、該上側絶縁層上に設けられた上側導
体層との繰返しにより形成される厚膜多層配線基
板において、前記下側導体層と中間導体層とが接
続される前記開口部の上に位置する前記上側導体
層部分に切欠き除去部を設けたことを特徴として
構成される。
The present invention provides a lower conductor layer provided on an insulator layer or on a substrate whose surface is at least an insulator;
a lower insulating layer formed to cover at least the lower conductor layer; a connection opening provided in the lower insulating layer so as to be located on the lower conductor layer;
an intermediate conductor layer provided on the lower insulating layer and connected to the lower conductor layer through the opening;
In a thick film multilayer wiring board formed by repeating an upper insulating layer provided to cover at least the intermediate insulating layer and an upper conductive layer provided on the upper insulating layer, the lower conductive layer and The structure is characterized in that a notch removal portion is provided in the upper conductor layer portion located above the opening to be connected to the intermediate conductor layer.
第1図a,bは本発明の一実施例の平面図及び
A−A′断面図である。
FIGS. 1a and 1b are a plan view and a sectional view taken along line A-A' of an embodiment of the present invention.
セラミツク基板1の上に下側導体層2を設け、
この下側導体層2を少くとも覆うように下側絶縁
層3を設ける。下側絶縁層3に接続用開口4を設
け、この開口4に例えば導体ペースト5を充填す
る。そして中間導体層6を下側絶縁層3の上に設
ける。そして、導体ペースト5を介して中間導体
層6を下側導体層2に電気的に接続する。次に、
中間導体層6を覆うように上側絶縁層7を設け
る。しかる後、上側絶縁層7の上に上側導体層8
を設ける。このとき、下側導体層2と中間導体層
との接続部となる開口4の上に位置する上側導体
層8の部分には切欠き除去部9を設けて、導体層
を存在せしめない。この切欠き除去部9を設ける
ことが、本発明の特徴である。 A lower conductor layer 2 is provided on a ceramic substrate 1,
A lower insulating layer 3 is provided to at least cover this lower conductor layer 2. A connection opening 4 is provided in the lower insulating layer 3, and the opening 4 is filled with, for example, a conductive paste 5. Then, an intermediate conductor layer 6 is provided on the lower insulating layer 3. Then, the intermediate conductor layer 6 is electrically connected to the lower conductor layer 2 via the conductor paste 5. next,
An upper insulating layer 7 is provided to cover the intermediate conductor layer 6. After that, an upper conductor layer 8 is formed on the upper insulating layer 7.
will be established. At this time, a notch removal portion 9 is provided in the portion of the upper conductor layer 8 located above the opening 4 that serves as the connection portion between the lower conductor layer 2 and the intermediate conductor layer, so that no conductor layer is present. Providing this notch removal portion 9 is a feature of the present invention.
このような構造にすると、たとえ開口4の上の
上側絶縁層7にピンホールがあつたとしても上側
導体層8はそのピンホールの所に形成しないか
ら、上側導体層8がピンホールを埋めて中間導体
層6に短絡するということは生じない。これによ
り従来の欠点が除去される。 With this structure, even if there is a pinhole in the upper insulating layer 7 above the opening 4, the upper conductor layer 8 will not be formed at the pinhole, so the upper conductor layer 8 will fill the pinhole. A short circuit to the intermediate conductor layer 6 does not occur. This eliminates the drawbacks of the prior art.
上記実施例では、基板のすぐ上の層について説
明したが、上側導体層8の上に絶縁層と導体層と
を重ねる多層配線にも同様に本発明は適用され、
この場合は、上側導体層8を下側導体層あるいは
中間導体層とみなすのである。 In the above embodiment, the layer immediately above the substrate was described, but the present invention is also applicable to multilayer wiring in which an insulating layer and a conductor layer are stacked on top of the upper conductor layer 8.
In this case, the upper conductor layer 8 is regarded as a lower conductor layer or an intermediate conductor layer.
以上詳細に説明したように、本発明によれば、
上側導体層と中間導体層もしくは下側配線層との
短絡を防いだ厚膜多層配線基板が得られるのでそ
の効果は大きい。
As explained in detail above, according to the present invention,
The effect is great because a thick film multilayer wiring board can be obtained that prevents short circuits between the upper conductor layer and the intermediate conductor layer or the lower wiring layer.
第1図a,bは本発明の一実施例の斜視図及び
断面図である。1……セラミツク基板、2……下
側導体層、3……下側絶縁層、4……開口、5…
…導体ペースト、6……中間導体層、7……上側
絶縁層、8……上側導体層、9……切欠き除去
部。
FIGS. 1a and 1b are a perspective view and a sectional view of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Ceramic substrate, 2... Lower conductor layer, 3... Lower insulating layer, 4... Opening, 5...
... Conductor paste, 6 ... Intermediate conductor layer, 7 ... Upper insulating layer, 8 ... Upper conductor layer, 9 ... Notch removal part.
Claims (1)
ある基板上に設けられた下側導体層と、少くとも
該下側導体層を覆うように形成された下側絶縁層
と、前記下側導体層上に位置するように前記下側
絶縁層に設けられた接続用の開口部と、前記下側
絶縁層の上に設けられかつ前記開口部を通して前
記下側導体層と接続する中間導体層と、少くとも
該中間絶縁層を覆うように設けられた上側絶縁層
と、該上側絶縁層上に設けられた上側導体層との
繰返しにより形成される厚膜多層配線基板におい
て、前記下側導体層と中間導体層とが接続される
前記開口部の上に位置する前記上側導体層部分に
切欠き除去部を設けたことを特徴とする厚膜多層
配線基板。1. A lower conductor layer provided on an insulator layer or on a substrate whose surface is an insulator, a lower insulating layer formed to cover at least the lower conductor layer, and the lower conductor. an intermediate conductor layer provided on the lower insulating layer and connected to the lower conductor layer through the opening; , in a thick film multilayer wiring board formed by repeating an upper insulating layer provided to cover at least the intermediate insulating layer and an upper conductive layer provided on the upper insulating layer, the lower conductive layer 1. A thick film multilayer wiring board, characterized in that a notch removal portion is provided in a portion of the upper conductor layer located above the opening to which the upper conductor layer and the intermediate conductor layer are connected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9093183A JPS59215796A (en) | 1983-05-24 | 1983-05-24 | Thick film multilayer circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9093183A JPS59215796A (en) | 1983-05-24 | 1983-05-24 | Thick film multilayer circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59215796A JPS59215796A (en) | 1984-12-05 |
JPH025023B2 true JPH025023B2 (en) | 1990-01-31 |
Family
ID=14012187
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9093183A Granted JPS59215796A (en) | 1983-05-24 | 1983-05-24 | Thick film multilayer circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59215796A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54135360A (en) * | 1978-04-13 | 1979-10-20 | Oki Electric Ind Co Ltd | Multiilayer ceramic board |
JPS57139996A (en) * | 1981-02-24 | 1982-08-30 | Nippon Electric Co | Hybrid multilayer circuit board |
JPS5873196A (en) * | 1981-10-27 | 1983-05-02 | 株式会社東芝 | Multilayer circuit board |
-
1983
- 1983-05-24 JP JP9093183A patent/JPS59215796A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54135360A (en) * | 1978-04-13 | 1979-10-20 | Oki Electric Ind Co Ltd | Multiilayer ceramic board |
JPS57139996A (en) * | 1981-02-24 | 1982-08-30 | Nippon Electric Co | Hybrid multilayer circuit board |
JPS5873196A (en) * | 1981-10-27 | 1983-05-02 | 株式会社東芝 | Multilayer circuit board |
Also Published As
Publication number | Publication date |
---|---|
JPS59215796A (en) | 1984-12-05 |
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