JPS5834772U - electrical circuit equipment - Google Patents

electrical circuit equipment

Info

Publication number
JPS5834772U
JPS5834772U JP12896081U JP12896081U JPS5834772U JP S5834772 U JPS5834772 U JP S5834772U JP 12896081 U JP12896081 U JP 12896081U JP 12896081 U JP12896081 U JP 12896081U JP S5834772 U JPS5834772 U JP S5834772U
Authority
JP
Japan
Prior art keywords
groove
brazing material
circuit
circuit boards
electrical circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12896081U
Other languages
Japanese (ja)
Inventor
功 秋山
Original Assignee
太陽誘電株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 太陽誘電株式会社 filed Critical 太陽誘電株式会社
Priority to JP12896081U priority Critical patent/JPS5834772U/en
Publication of JPS5834772U publication Critical patent/JPS5834772U/en
Pending legal-status Critical Current

Links

Landscapes

  • Combinations Of Printed Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の回路装置の一部を説明的に示す斜視図で
ある。第2図〜第8図は本考案の実施例に係わる回路装
置の一部を説明的に示すものであり、第2図は分割前の
基板を示す平面図、第3図は第2図の基板の底面図、第
4図は基板に回路素子及びリード部材を結合した状態を
示す平面図、第5図は第1及び第2の回路基板を分割し
て積層した状態を示す平面図、第6図は第5図のVI−
VI線断面図、第7図は第5図の積層体に半田を被着さ
せた状態を示す平面図、第8図は第7図の積層体を説明
的に示す斜視図である。 尚図面に用いられている符号に於いて、11は第1の回
路基板、12は第2の回路基板、13は貫通孔、13a
は上の溝、13bは下の溝、14はスリット、17は第
1の回路導体、18は第2の回路導体、19は導体被膜
、24は接着材、25は半田である。 第6図 12 第7図 3125
FIG. 1 is a perspective view illustrating a part of a conventional circuit device. 2 to 8 are explanatory diagrams of a part of the circuit device according to the embodiment of the present invention. FIG. 2 is a plan view showing the board before division, and FIG. FIG. 4 is a bottom view of the board; FIG. 4 is a plan view showing a state in which circuit elements and lead members are coupled to the board; FIG. 5 is a plan view showing a state in which the first and second circuit boards are separated and stacked; Figure 6 shows VI- of Figure 5.
7 is a plan view showing a state in which the laminate shown in FIG. 5 is coated with solder; and FIG. 8 is a perspective view illustrating the laminate shown in FIG. 7. In the symbols used in the drawings, 11 is the first circuit board, 12 is the second circuit board, 13 is the through hole, 13a
13b is an upper groove, 13b is a lower groove, 14 is a slit, 17 is a first circuit conductor, 18 is a second circuit conductor, 19 is a conductive film, 24 is an adhesive, and 25 is a solder. Figure 6 12 Figure 7 3125

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)複数の回路基板が積層接着され、前記複数の回路
基板の端部に前記複数の回路基板を連通ずる溝が設けら
れ、前記溝の壁面に後記のろう材を付着させることが可
能な導体被膜が形成され、前記回路基板の主面に設けら
れた回路導体が前記溝の前記導体被膜に接続され、前記
溝の前記導体被膜にろう材が被着され、前記ろう材によ
り前記複数の回路基板の相互間の電気的接続がなされて
いることを特徴とする電気回路装置。
(1) A plurality of circuit boards are laminated and bonded, a groove is provided at the end of the plurality of circuit boards to communicate the plurality of circuit boards, and a brazing material described below can be attached to the wall surface of the groove. A conductive coating is formed, a circuit conductor provided on the main surface of the circuit board is connected to the conductive coating in the groove, a brazing material is applied to the conductive coating in the groove, and the brazing material connects the plurality of An electric circuit device characterized in that circuit boards are electrically connected to each other.
(2)前記ろう材は半田である実用新案登録請求の範囲
第1項記載の電気回路装置。
(2) The electric circuit device according to claim 1, wherein the brazing material is solder.
JP12896081U 1981-08-31 1981-08-31 electrical circuit equipment Pending JPS5834772U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12896081U JPS5834772U (en) 1981-08-31 1981-08-31 electrical circuit equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12896081U JPS5834772U (en) 1981-08-31 1981-08-31 electrical circuit equipment

Publications (1)

Publication Number Publication Date
JPS5834772U true JPS5834772U (en) 1983-03-07

Family

ID=29922639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12896081U Pending JPS5834772U (en) 1981-08-31 1981-08-31 electrical circuit equipment

Country Status (1)

Country Link
JP (1) JPS5834772U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6046090A (en) * 1983-08-24 1985-03-12 シヤ−プ株式会社 Electronic circuit board
JPS6454364U (en) * 1987-09-30 1989-04-04

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494156A (en) * 1972-05-01 1974-01-14
JPS5258468A (en) * 1975-11-10 1977-05-13 Hitachi Ltd Production of ceramic package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494156A (en) * 1972-05-01 1974-01-14
JPS5258468A (en) * 1975-11-10 1977-05-13 Hitachi Ltd Production of ceramic package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6046090A (en) * 1983-08-24 1985-03-12 シヤ−プ株式会社 Electronic circuit board
JPS6454364U (en) * 1987-09-30 1989-04-04

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