JPH0442960Y2 - - Google Patents

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Publication number
JPH0442960Y2
JPH0442960Y2 JP1986032588U JP3258886U JPH0442960Y2 JP H0442960 Y2 JPH0442960 Y2 JP H0442960Y2 JP 1986032588 U JP1986032588 U JP 1986032588U JP 3258886 U JP3258886 U JP 3258886U JP H0442960 Y2 JPH0442960 Y2 JP H0442960Y2
Authority
JP
Japan
Prior art keywords
circuit
copper foil
ground
shield layer
mesh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1986032588U
Other languages
Japanese (ja)
Other versions
JPS62145400U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986032588U priority Critical patent/JPH0442960Y2/ja
Publication of JPS62145400U publication Critical patent/JPS62145400U/ja
Application granted granted Critical
Publication of JPH0442960Y2 publication Critical patent/JPH0442960Y2/ja
Expired legal-status Critical Current

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  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structure Of Printed Boards (AREA)
  • Insulated Conductors (AREA)

Description

【考案の詳細な説明】 [産業上の利用分野] 本考案はシールド付フレキシブル配線板にかか
わる。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a shielded flexible wiring board.

[従来の技術と問題点] 従来、シールド付プリント配線板として、第3
図イ,ロに示すように、フレキシブルなベース絶
縁フイルムに接着した銅箔をエツチングして回路
を形成する際、一側にベタ銅箔を残しておき、回
路を絶縁した後、ベタ銅箔を回路上に折りたた
み、上下を覆つてシールドする構成が考えられて
いた。
[Conventional technology and problems] Conventionally, as a shielded printed wiring board, the third
As shown in Figures A and B, when forming a circuit by etching copper foil adhered to a flexible base insulating film, a solid copper foil is left on one side, and after insulating the circuit, the solid copper foil is removed. The idea was to fold it over the circuit and cover the top and bottom to shield it.

図において、1はベース絶縁フイルム、12は
信号回路、13はベタ銅箔、14は絶縁カバーレ
イである。
In the figure, 1 is a base insulating film, 12 is a signal circuit, 13 is a solid copper foil, and 14 is an insulating coverlay.

ところで、シールド層との接続のため、信号回
路間にアース回路を入れてもシールド層との接続
が困難であり、アース回路とシールド層の接続は
回路端のみで行うようにするため、シールド効果
が低く、又ロ図に示すように、3層間が一体化し
ないため、静電容量が安定せず、又屈曲によりベ
タ銅箔にしわが発生し、ベタ銅箔のため信号回路
とアース間に静電容量が大きく、信号回路とアー
ス回路間が一定せず、クロストークが大きかつ
た。また屈曲性も悪い。
By the way, because of the connection with the shield layer, even if you insert a ground circuit between the signal circuits, it is difficult to connect with the shield layer, and since the ground circuit and the shield layer are connected only at the circuit ends, the shielding effect Furthermore, as shown in Figure 2, the capacitance is unstable because the three layers are not integrated, and wrinkles occur in the solid copper foil due to bending. The capacitance was large, and the connection between the signal circuit and the ground circuit was inconsistent, resulting in large crosstalk. It also has poor flexibility.

[考案の目的・構成] 本考案は、上述の欠点を排し、特に静電容量を
一定とし、外部からの電磁シールド効果を備える
フレキシブル配線板(以下FPCという)を得る
ことにあり、信号回路に隣接するアース回路が、
前記信号回路の上下を平行に走るメツシユ状のシ
ールド層と接続され、前記メツシユ状のシールド
層の、前記両回路に対する上部、下部の銅箔残存
率が前記回路面積とほぼ等しくなるようにエツチ
ングにより開孔されたことに特徴を有するもので
ある。
[Purpose and structure of the invention] The purpose of the invention is to eliminate the above-mentioned drawbacks, and to obtain a flexible wiring board (hereinafter referred to as FPC) that has constant capacitance and has an electromagnetic shielding effect from the outside. The ground circuit adjacent to
It is connected to a mesh-shaped shield layer running parallel to the top and bottom of the signal circuit, and is etched so that the copper foil remaining ratio of the upper and lower portions of the mesh-shaped shield layer with respect to both the circuits is approximately equal to the circuit area. It is characterized by having holes.

以下第1図に示す実施例及び第2図に示す実施
例外観図により、本考案を説明する。
The present invention will be explained below with reference to an embodiment shown in FIG. 1 and an external view of the embodiment shown in FIG.

第1図は断面を示している。図において、1は
ベース絶縁フイルム、2はベース接着剤を示し、
3は信号回路、4はアース回路、5はメツシユ状
シールド層、6はカバーレイフイルム、7はカバ
ーレイ接着剤、8はシールド層5とアース回路4
との導電接着部を示し、ベース絶縁フイルム1に
接着した銅箔の一側にエツチングにより形成され
た信号回路3、アース回路4にカバーレイフイル
ム6を接着し、前記銅箔上の他側にエツチングに
より形成されたメツシユ状の銅箔をシールド層と
して前記信号回路3、アース回路4をとりまいて
かぶせ、3層一体化したフレキシブル配線板であ
つて、前記アース回路4とメツシユ状銅箔による
シールド層5は前記ベース絶縁フイルム1、カバ
ーレイフイルム6にあけた複数のグランド穴を通
して電気接続され、前記メツシユ状シールド層5
の、前記両回路に対する上部、下部の銅箔残存率
が前記両回路面積とほぼ等しいか、やや大きくな
るように前記シールド層に開孔されているもので
ある。
FIG. 1 shows a cross section. In the figure, 1 indicates the base insulating film, 2 indicates the base adhesive,
3 is a signal circuit, 4 is a ground circuit, 5 is a mesh-like shield layer, 6 is a coverlay film, 7 is a coverlay adhesive, 8 is the shield layer 5 and the ground circuit 4
A cover lay film 6 is bonded to the signal circuit 3 and ground circuit 4 formed by etching on one side of the copper foil bonded to the base insulating film 1, and the cover lay film 6 is bonded to the other side of the copper foil. The signal circuit 3 and the ground circuit 4 are surrounded and covered with a mesh-shaped copper foil formed by etching as a shield layer to form a three-layer integrated flexible wiring board. The shield layer 5 is electrically connected to the base insulating film 1 and the cover lay film 6 through a plurality of ground holes.
The holes are formed in the shield layer so that the copper foil remaining ratios of the upper and lower parts of both circuits are approximately equal to or slightly larger than the areas of both circuits.

ベース絶縁フイルム1として、例えばポリイミ
ドフイルム、ポリパラバン酸フイルム、ポリエス
テルフイルム等から選択し、これに接着剤を、例
えばエポキシ系、ウレタン系、フエノール系、ブ
チラール系、トリアジン系等から選択して、18〜
70μの電解、圧延による銅箔を接着した基板に所
定任意のパターンをエツチングにより回路を形成
する。
The base insulating film 1 is selected from, for example, polyimide film, polyparabanic acid film, polyester film, etc., and an adhesive is selected from, for example, epoxy type, urethane type, phenol type, butyral type, triazine type, etc.
A circuit is formed by etching a predetermined arbitrary pattern on a substrate to which a 70μ electrolytic and rolled copper foil is adhered.

回路として、図示のように信号回路3とアース
回路4を設けるが、信号回路3の隣接部には必ず
アース回路4を設ける。前記隣接部というのは、
信号回路3の本数3本目の次か、それ以内にアー
ス回路4があることを意味している。
As circuits, a signal circuit 3 and a ground circuit 4 are provided as shown in the figure, and the ground circuit 4 is always provided adjacent to the signal circuit 3. The adjacent portion is
This means that the ground circuit 4 is located next to or within the third signal circuit 3.

アース回路4には上下のメツシユ状シールド層
5と接続するためのグランド穴を設け、導電性材
料で導通する。
The ground circuit 4 is provided with a ground hole for connection to the upper and lower mesh-shaped shield layers 5, and is electrically connected with a conductive material.

導電性材料としては、半田付け、半田クリーム
や銀ペースト、銅ペースト、カーボンペースト等
の樹脂を用い、グランド穴に充填して、その後、
後述のシールド層5と導電接続される。
As the conductive material, use soldering, solder cream, resin such as silver paste, copper paste, carbon paste, etc., fill the ground hole, and then
It is electrically connected to a shield layer 5, which will be described later.

シールド層5は、回路形成時に、エツチングに
よりメツシユ状に形成される。メツシユ状のしや
へい銅箔残存率は回路面積とほぼ等しいか、やや
大きい目がよい。銅箔残存率による面積が回路面
積より小さいとシールド効果が低くなり又大きす
ぎるとクロストークが大きくなるためである。
The shield layer 5 is formed into a mesh shape by etching during circuit formation. It is preferable that the residual ratio of the mesh-shaped shriveled copper foil be approximately equal to or slightly larger than the circuit area. This is because if the area determined by the copper foil residual rate is smaller than the circuit area, the shielding effect will be lowered, and if it is too large, crosstalk will increase.

信号回路3は、カバーレイ接着剤7とカバーレ
イフイルム6によつて絶縁され、その後メツシユ
状のシールド層5で覆われる。
The signal circuit 3 is insulated by a coverlay adhesive 7 and a coverlay film 6, and then covered with a mesh-shaped shield layer 5.

[試作例] 25μ厚のポリイミドフイルムにエポキシ接着剤
25μを塗布、乾燥し、その後アース回路のグラン
ド位置に各2ケ所の穴開けを行ない、35μの電解
銅箔をラミネートしてFPC基板を得た。
[Prototype example] Epoxy adhesive on 25μ thick polyimide film
After applying a 25μ film and drying it, two holes were made at each ground position of the earth circuit, and a 35μ electrolytic copper foil was laminated to obtain an FPC board.

グランド穴にパターンを合わせ、0.3mmの信号
回路2本ごとに1本のアース回路を形成し、各々
の回路間は0.25mmとした。さらにシールド層の銅
箔残存率は、回路面積とほぼ等しい55%となるよ
うに1.0mmφの穴を1.4mmピツチでエツチングによ
り開孔し、メツシユ状にした。ここで言うシール
ド層の銅箔残存率は信号回路とアース回路の上部
又は、下部におおいかぶさるしやへい銅箔の残存
率であり、回路面積とはしやへい銅箔の内部に入
る銅箔部分においてエツチングにより形成された
信号回路とアース回路全体を言う。
The pattern was aligned with the ground hole, one ground circuit was formed for every two 0.3 mm signal circuits, and the distance between each circuit was 0.25 mm. Furthermore, holes of 1.0 mm diameter were opened at a pitch of 1.4 mm by etching to form a mesh so that the copper foil remaining rate of the shield layer was 55%, which was approximately equal to the circuit area. The copper foil survival rate of the shield layer referred to here is the survival rate of the copper foil that covers the top or bottom of the signal circuit and the ground circuit, and the circuit area and the copper foil that goes inside the copper foil. Refers to the entire signal circuit and ground circuit formed by etching in a portion.

言いかえればしやへい銅箔の開孔度と回路間隔
の面積とはほぼ等しいことを言う。
In other words, the degree of aperture in the copper foil and the area of the circuit spacing are approximately equal.

その後、25μ厚のポリイミドフイルムよりなる
カバーレイフイルムにエポキシ接着剤を30μ塗布
し、グランド穴及び端子部が露出するように打抜
き、前述の信号回路及びアース回路上に接着させ
た。
Thereafter, 30 μm of epoxy adhesive was applied to a coverlay film made of polyimide film with a thickness of 25 μm, punched out so that the ground hole and terminal portion were exposed, and the film was adhered onto the signal circuit and ground circuit described above.

接着後、ベース絶縁フイルム及びカバーレイフ
イルム上のグランド穴に導電性銀ペーストを充填
し、アース回路がシールド層との導通をとれる状
態とした。
After adhesion, the ground holes on the base insulating film and coverlay film were filled with conductive silver paste, so that the ground circuit could be electrically connected to the shield layer.

その後、シールド層は銅箔面を内側にして信号
回路面と面するように折りたたみ、導電性銀ペー
ストによる導電性接着部で、アース回路とシール
ド層が接触するようにし、中の信号、アース回路
と上、下のシールド層よりなる3層を一体化し、
3層が平行になるよういプレス成形した。
After that, the shield layer is folded so that the copper foil side faces the signal circuit side, and the ground circuit and the shield layer are in contact with the conductive adhesive made of conductive silver paste. The three layers consisting of the upper and lower shield layers are integrated,
Press molding was performed so that the three layers were parallel to each other.

得られたシールド付FPCについて、信号回路
とアース回路間の静電容量及び電磁シールド効果
を測定した。その結果、静電容量は130PF/mと
低く、シールド効果もシールドのないFPCに比
べ30dB以上減衰することが判つた。
Regarding the obtained shielded FPC, the capacitance between the signal circuit and the ground circuit and the electromagnetic shielding effect were measured. As a result, the capacitance was as low as 130PF/m, and the shielding effect was found to be attenuated by more than 30dB compared to an unshielded FPC.

又本シールド付FPCを260℃の半田槽につけて
も、180°屈曲してもシールド効果は変化せず、安
定したシールド付FPCであることを確認した。
Furthermore, even when this shielded FPC was placed in a soldering bath at 260°C or bent 180°, the shielding effect did not change, confirming that it is a stable shielded FPC.

[考案の効果] シールド槽の前記両回路に対する上部、下部の
銅箔残存率を回路面積とがほぼ等しいかやや大き
くしているのでクロストークがなくなる。
[Effects of the invention] Crosstalk is eliminated because the copper foil remaining ratios of the upper and lower portions of the shield tank for both circuits are approximately equal to or slightly larger than the circuit area.

信号回路とシールド層は平行であるので静電容
量を一定にする。
Since the signal circuit and the shield layer are parallel, the capacitance is kept constant.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案実施例を断面で示す。第2図は
実施例外観を示す。第3図イは従来のフレキシブ
ル配線板展開図を示し、同ロはイの配線板を折り
たたんでシールド付FPCとして形成された配線
板を示す。 1……ベース絶縁フイルム、3……信号回路、
4……アース回路、5……メツシユ状シールド
層、6……カバーレイフイルム。
FIG. 1 shows an embodiment of the invention in cross section. FIG. 2 shows the external appearance of the embodiment. Figure 3A shows a developed view of a conventional flexible wiring board, and Figure 3B shows a wiring board formed by folding the wiring board of A to form a shielded FPC. 1...Base insulation film, 3...Signal circuit,
4...Earth circuit, 5...Mesh-shaped shield layer, 6...Coverlay film.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ベース絶縁フイルムに接着した銅箔の一側に形
成された信号回路、アース回路にカバーレイフイ
ルムを接着し、前記銅箔上の他側に形成されたメ
ツシユ状の銅箔をシールド層として前記信号回
路、アース回路をとりまいてかぶせて3層一体化
したフレキシブル配線板であつて、前記アース回
路とメツシユ状銅箔によるシールド層は前記ベー
ス絶縁フイルム、カバーレイフイルムにあけた複
数のグランド穴を通して電気接続され、前記メツ
シユ状シールド層の前記両回路に対する上部、下
部の銅箔残存率が前記信号回路およびアース回路
面積とほぼ等しいか、やや大きくなるように、前
記銅箔にエツチングによりメツシユ状に開孔され
ていることを特徴とするシールド付フレキシブル
配線板。
A cover lay film is bonded to the signal circuit and ground circuit formed on one side of the copper foil bonded to the base insulating film, and the mesh-shaped copper foil formed on the other side of the copper foil is used as a shield layer to signal the signal. It is a flexible wiring board that integrates three layers by surrounding and covering a circuit and a ground circuit, and the ground circuit and the shield layer made of mesh copper foil are connected through a plurality of ground holes drilled in the base insulating film and the cover lay film. electrically connected, and the copper foil is etched into a mesh shape so that the residual ratio of the copper foil on the upper and lower parts of the mesh shield layer with respect to both circuits is approximately equal to or slightly larger than the area of the signal circuit and the ground circuit. A flexible wiring board with a shield characterized by having holes.
JP1986032588U 1986-03-06 1986-03-06 Expired JPH0442960Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986032588U JPH0442960Y2 (en) 1986-03-06 1986-03-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986032588U JPH0442960Y2 (en) 1986-03-06 1986-03-06

Publications (2)

Publication Number Publication Date
JPS62145400U JPS62145400U (en) 1987-09-12
JPH0442960Y2 true JPH0442960Y2 (en) 1992-10-12

Family

ID=30839409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986032588U Expired JPH0442960Y2 (en) 1986-03-06 1986-03-06

Country Status (1)

Country Link
JP (1) JPH0442960Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011096599A (en) * 2009-11-02 2011-05-12 Sumitomo Electric Ind Ltd Shielded flat cable and method of manufacturing the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5292027B2 (en) * 2008-09-09 2013-09-18 信越ポリマー株式会社 Optical transceiver
WO2010103722A1 (en) * 2009-03-10 2010-09-16 住友ベークライト株式会社 Circuit board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848499A (en) * 1981-09-17 1983-03-22 住友電気工業株式会社 Electronic circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5451362U (en) * 1977-09-19 1979-04-09
JPS58116262U (en) * 1982-01-30 1983-08-08 日本メクトロン株式会社 Flexible circuit board with shield structure
JPH0132392Y2 (en) * 1984-12-17 1989-10-03

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848499A (en) * 1981-09-17 1983-03-22 住友電気工業株式会社 Electronic circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011096599A (en) * 2009-11-02 2011-05-12 Sumitomo Electric Ind Ltd Shielded flat cable and method of manufacturing the same

Also Published As

Publication number Publication date
JPS62145400U (en) 1987-09-12

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