JPS5873196A - Multilayer circuit board - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a multilayer wiring board in which electrical wiring is achieved by alternately forming conductor layers and insulating layers to achieve specific circuit performance.

(2) Prior art In recent years, there has been a marked increase in demand for various electronic devices to be smaller, lighter, faster, and more reliable.

As a method of adding up these waterings, the multi-chidzo/mother-tsuke-song technique has been developed. If this happens, the conductive pattern J- and the insulating layer are printed by printing the entire paste 1 on the alumina ceramic substrate, drying and firing, printing the insulating paste on top of it, drying and firing, and repeating the process. The so-called thick film printing method, in which conductive paste and insulating paste are alternately laminated on a green sheet, or the printed laminated metallized ceramic substrate method, in which conductive paste and insulating paste are repeatedly laminated in a dry state on a green sheet, and then simultaneously fired in a reducing atmosphere furnace. On the high-security multilayer wiring board,
! This is a technology that mounts multiple chip components and hermetically seals the whole thing.7 This type of multi-layer wiring board for multi-layer wiring boards is made by mounting multiple chip components and sealing the whole thing hermetically. - As shown in FIG. 1 (-), 7' parts such as IC tags or capacitor chips, binding pads 12 and 13 for the machine, and a carrier for hermetically sealing the whole.
M-mounting etc. - Methi, Kushiel No. 9 turn 1
4. A conductor green having relatively large (8) holes compared to the line width of the lower layer conductor 9 turns 16 as shown in the figure 4, and an outer conductor that should be electrically connected to the inner lead gonding node of the IC chip. It is formed in a mixture of conductor patterns having a relatively small area, which is approximately the same as or slightly larger than the line width of the underlying conductor pattern 16, such as lead non-dings and nine leads 15. On the other hand, the fourth turn 16 of the lower conductor to be electrically connected to these nine turns 12 to 15 of the surface conductor is connected through an insulator layer 17 having a through hole 18 as shown in FIG. 1(b). The insulator layer 17 is usually formed to ensure dielectric strength between the conductor patterns 12 to 15 and the lower conductor pattern 16, and to ensure no gaps 7" due to pinholes in the insulator layer 17.
-) In order to prevent accidents, an insulator layer 17iJ) having a thickness of 2 times was formed by printing twice, or an insulator l- having a thickness of 3 layers by printing three times.

(3) Problems with the Prior Art In the structure shown in FIG. 1, there are no major problems in the case of the conductor/volume turns 15 having a relatively small area, but the surface conductor main turns 12, 13, . . . having a relatively large area. In No. 14, there is a very high probability that an interlayer short circuit will occur between the conductor in the lower layer and the 9th turn, which is a factor that seriously reduces the performance of such a multilayer wiring board. In addition, during the manufacturing of multilayer wiring boards, pinholes may exist in the insulator layer 17 even if they do not result in interlayer short circuits. Due to the change, an interlayer short circuit occurs at the pinhole part, and there is also a problem with reliability (3).

In order to prevent such interlayer short-circuit behavior, the thickness of the insulating layer 17 existing between the surface conductor vine turns 12 to 15 and the lower conductor/9 turf 16 layer should be further increased.
What is formed by conventional two- or three-time printing is
It is conceivable to change to printing once or four times. However, in that case, the through hole J8 is crushed due to misalignment during printing or sagging of the loquat paste, and the conductor turfs 12 to 15 and the lower conductor turf 1 are crushed.
6 will no longer be electrically connected, which will result in a decrease in the yield of the multilayer wiring board in another respect.

(4) Purpose of the Invention The purpose of the present invention is to improve the connection between the conductors and turns of the uppermost layer having various areas and the conductors and turns of the lower layer 11i1)*l&'l
It is an object of the present invention to provide a multilayer wiring board that has fewer seat accidents and electrical failure accidents, and can improve yield and achieve high reliability.

(5) Contract of the invention The present invention provides a conductor mother turf 1-, an insulating layer and a force;
A multi-layer wiring consisting of a first conductor mother turn which is laminated and has a comparatively large area over the top layer conductor f-turn layer 75, and a relatively small second conductor 9 turns. On the board, among the insulators 1- between the conductor pattern layer of the uppermost 1- layer of the No. 6 revision and the lower layer conductor/4' turn +@, the conductor of the first ridge of Tsumugi ! The % characteristic is that at least one layer of galvanic insulator j- is provided directly below the turn.

(6J Effects of the Invention According to the present invention, there is a probability that there will be an interlayer short circuit with the conductor pattern j- in the lower layer among the first and second conductor patterns constituting the conductor pattern 1- in the uppermost layer. Additional insulators are added only directly under the conductor/lean of 1a [which tends to occur depending on the situation]
By providing this, it is possible to reduce the number of short-circuit accidents between 1 and 2 on the entire multilayer wiring board, and at the same time, it is possible to reduce as much as possible the number of electrical connection failures between the conductor and the toe turns in critical areas. It becomes possible to meet the requirements of

(7) Embodiment of the invention FIG. 2 shows an embodiment of the invention, in which 21 is an alumina ceramic substrate, 26 is a lower conductor no.
Reference numeral 27 indicates the uppermost insulator layer. Conductor turns 22 to 26 forming the uppermost conductor pattern layer
Of these, 22 are IC chips, die-dending pads for mounting f, 23 are capacitor chips, etc.! 24 is the gear for mounting the whole body, the harness for mounting the f, the inner lead bunding for the kushir, 25 is the inner lead bunding for the IC te, g.
, P shows an outer lead gonding node to be electrically connected to P. Here, conductor mother turn 2
Reference numerals 2 to 24 denote first conductor patterns having a relatively larger area than the lower layer conductor lean 26, and 25 denotes a 2m-th conductor pattern having a relatively small area compared to this.

Then, the first m-th conductor/mother turn 22 of the insulating layer 27
An additional insulator layer 29 is provided over the portion immediately below 24 . That is, this insulating layer 29 is formed except for the part where the second type conductor pattern 25 is present, that is, the first type conductor pattern 25 is
It is formed by selectively printing an insulating paste one or more times only on the lower part of the seed conductor f-turns 22-24.

Note that this additional insulator layer 2g is formed one size larger than the first type conductor turns 22 to 24, and due to positional deviation during printing, the first type conductor turns 22 to 24
It is desirable that the insulator layer 29 not protrude from the additional insulator layer 29.

In addition, when the conductor 9 turns 22 to 24 of the first rod and the conductor 26 of the lower layer are formed on the lower layer insulator fWIz7 and are electrically connected through the 9 through holes 28, the additional insulator layer 2g The diameter of the through hole 30 to be formed is set to be larger than the diameter of the through hole 28 in the lower insulating layer 27, so as to avoid sagging of the insulating paste during printing and the printing position due to the addition of the insulating layer 29. It is desirable to form the structure in such a way that electrical connection failures due to misalignment do not occur.1 As described above, according to the present invention, it is possible to reduce interlayer short circuit accidents and interlayer electrical connection failure accidents. 9. Improvement of manufacturing yield of multilayer wiring board and multi-chig using this. Contribute to improved reliability of turns or sleep.

In addition, in the example, as an example of the second conductor and 9 turns,
Although outer lead bonding is used as an example, the present invention is not limited to this and may be a simple wiring conductor.

[Brief explanation of the drawing]

Figures 1 (a) and (b) are a plan view and A-A' cross-sectional view of a conventional multi-layer wiring board;
are a plan view of a multilayer wiring board according to an embodiment of the invention, and A-A'l! ;j'r view. 11, 21-Insulating substrate such as alumina ceramic, 1
6.26...lower J- conductor/lean, 17°27...
・Lower 1- insulator 1-118.21j...Through hole in the lower j@ insulator layer, 12-14.22-24...1'lIi with relatively steep surface t- conductor/? turn, 1
5.25... Second conductor pattern having a relatively small area, 29... Additional insulator rd, go... Through hole of additional insulator 1-.

Claims (5)

[Claims] (1) The 4-turn conductor layer and the insulator layer are alternately laminated, and the 4-turn conductor layer on the top layer has a comparatively large area, and the 1m conductor arm turn has a relatively small area. @ In a multilayer wiring board that includes 2 conductors and 9 turns, the top layer conductor 4
The turn layer and the lower salary! A multi-wiring board characterized in that an additional insulating layer of at least -J- is provided in a portion of the insulating layer between the turn layer and the conductor mother turn of the first lance immediately below the conductor mother turn. (2) The first type of conductor/4' turn is a guiding pad for mounting a chip component, as claimed in claim 1. (3) The multilayer wiring board according to claim 1, wherein the nine turns of the conductor in the first package are patterns for a methic seal. (4) A claim characterized in that the size of the additional insulator j- is larger than the size of the first conductor, 9 turns. (5) Additional fiI! A characteristic feature of the three-layer insulator layer is that it has holes with a larger diameter than the holes formed in the underlying insulator layer. F. A multilayer wiring board according to claim 1.