JP2001326462A - Printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem where arrangement of a component like a QFP in which a large number of wirings exist, on a fourth layer is difficult since the fourth layer is a power source or a GND layer, in a layer constitution in which a first layer and a second layer must be made signal layers, a third layer must be made a GND layer or a power source layer, and the fourth layer must be made a power source layer or a GND layer, when a chip size package LSI and a QFP-LSI which are arranged on the first layer are connected by using a partial VIA hole which has a small VIA diameter and is used for connecting a part between adjacent layers in a four-layer printed wiring board. SOLUTION: In a layer constitution of a region where a chip size package LSI and a QFP-LSI on a first layer are connected, the first layer and a second layer are made the signal layers, a third layer is made the GND layer, and a fourth layer is made the power source layer. In the other region, the first layer and the fourth layer are made signal layers, the third layer is made a GND layer, and the second layer is made a power source layer. A part between the power source layers of both of the regions is connected by using a penetrating VIA hole. As a result, the GND layers can be made flat, and arrangement and wiring on the fourth layer of a component like the QFP in which a large number of wirings exist is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board, in particular, a four-layer wiring board, in which the terminals of the LSI are arranged in a lattice pattern on the back surface of the package and the terminals of the LSI are arranged in one line on four sides of a rectangular package And a method of connecting terminals of packages arranged in the same manner.

[0002]

2. Description of the Related Art A conventional printed wiring board is composed of one or more electric conductor wiring layers such as copper and an electric insulator.

However, in recent high-density printed wiring boards, in order to make the component mounting area close to the area of the printed wiring board, N (N is an integer that satisfies N ≧ 1) electric conductor wiring layers and N electric conductor wiring layers are used. N-1 (in the case of N-1 = 0, N-1 = 1) layer electrical insulator is interposed therebetween, and N-1
By configuring the layer printed wiring board and determining the type of wiring to be assigned in each wiring layer, compared to the case of a single layer wiring board,
The area for wiring can be increased by N-2 times to N times.

For example, when N = 4 in the printed wiring board, that is, in the case of a four-layer printed wiring board, the first
The layer and the fourth layer mainly connect wires for passing digital and analog electric signals, the second layer is a layer for passing wires for supplying power to the circuit, that is, a power supply layer, and the third layer is a reference for the circuit. It is used as a layer through which a reference potential wiring for determining a potential, that is, a GND layer.

As a result, the number of layers for wiring electric signals can be allocated to two layers, which is twice as large as that of a single-layer wiring board. When electric signals are connected to all the layers from the first layer to the fourth layer by passing electric signals also to the power supply layer and the GND layer, the area is up to four times as large as that of the single-layer wiring board. Can be used for electrical signal wiring.

In order to connect different layers, a hole having a small diameter is provided in the printed wiring board, and copper plating is applied to an inner wall surface of the hole to form a structure called a VIA hole which secures electrical conductivity in the vertical direction. Provided.

[0007] As for the VIA hole, a penetrating VIA hole penetrating through all layers from the first layer to the Nth layer and electrically connecting to a desired layer, and a through hole is formed only in two adjacent layers, and the inner wall surface is formed. There is a portion VIA hole filled with copper plating or conductive paste, and in general, the portion VIA hole does not penetrate the hole, so that the degree of freedom of component arrangement increases.

Further, the through-via hole is formed from the first layer to the Nth layer.
Since it is necessary to penetrate to the layer and electrically conduct with a desired layer, it is necessary to perform a drilling process by accurately aligning the positions of the first to Nth layers.

On the other hand, the partial VIA hole is formed by first preparing semi-finished products of two adjacent printed wiring boards to be made conductive, performing perforation processing, and then laminating a plurality of perforated processed semi-finished products. VIA to be created
The processing accuracy of the hole itself only needs to match the position of the two layers.

[0010] As a result, the diameter of the land existing around the partial VIA hole can be smaller than the land diameter of the penetrating VIA hole, and the VIA can be formed even in a place where the lands for mounting the components are dense. Part V of the hole
By using the IA hole, a VIA hole can be formed.

On the other hand, the size of the LSI mounted on these printed wiring boards has also been reduced in size.

[0012] From a package called a quadruple package (QFP), which is a rectangular plastic package for protecting an internal semiconductor chip, in which lead wires of a plurality of conductors connected to the internal semiconductor chip are arranged in four lines on four sides, In recent years, balls made of a solder alloy or the like are arranged in a grid pattern on the bottom surface of a chip or a base material directly from the bottom surface of a semiconductor chip or indirectly with a base material such as ceramic interposed therebetween. Chip-size packages configured to be connected to external circuits have been put into practical use. In response to the reduction in package size, that is, the reduction of the mounting area, and the increase in the number of terminals due to the multifunctionalization of LSI. I have.

[0013] A chip size package LSI is used in a printed circuit board in which a chip size package and a QFP are mixed using the conventional printed circuit board as described above.
FIG. 8 shows a state in which wiring is extracted from the wiring and wired to the LSI of the QFP.

In FIG. 8, 1 is a chip size package LSI, and 11 is the chip size package LSI.
1 is a solder ball for a GND terminal; 12 is a solder ball for a power terminal of the chip-size package LSI 1;
Reference numerals 4 and 15 denote solder balls for signal terminals of the chip size package LSI1, and reference numeral 16 denotes a bypass capacitor inserted between the power supply of the chip size package LSI1 and GND.

2 is a QFP-LSI, 21 is a terminal of the QFP-LSI 2, and 22 is a QFP-LSI.
2 and a bypass capacitor inserted between GND and
Reference numeral 23 denotes a terminal which is not directly involved in connecting the QFP-LSI 2 to the chip size package LSI 1;
Is a QFP-LSI placed on the back of QFP-LSI2
Is shown.

Reference numeral 3 denotes a six-layer printed wiring board, and 311
To 315 are patterns of the first layer of the printed wiring board 3, 32 is a pattern of the second layer of the printed wiring board 3, 33 is a pattern of the third layer of the printed wiring board 3, and 34 is the printed pattern. The pattern of the fourth layer of the wiring board 3 is shown, and 361 to 365 show the pattern of the sixth layer of the printed wiring board 3.

Reference numerals 91, 92, 95, and 96 denote through-via holes provided in the printed wiring board 3, respectively.
Indicates a partial VIA hole provided in the printed wiring board 3 for connecting the first layer and the second layer.

Reference numeral 301 denotes an electrical insulator that insulates the first layer patterns 311 to 315 provided on the printed wiring board 3 from the second layer pattern 32;
Reference numerals 2, 303, 304, and 305 denote, respectively, between the second layer pattern 32 and the third layer pattern 33, between the third layer pattern 33 and the fourth layer pattern 34, and between the fourth layer pattern 34 and the fifth An electrical insulator that insulates between the layer patterns and between the fifth layer pattern and the sixth layer patterns 361 to 365.

The third layer pattern 33 is a power supply layer for supplying power to the chip size package LSI1 and the QFP-LSI2, and the fourth layer pattern 34 is a chip size package LSI1 and the QFP-LSI
2 is a GND layer for setting reference potentials 2 and 24.

The bypass capacitors 16, 22 and the QFP-LSI 24 are arranged in a sixth layer, and the chip size package LSI1 and the QFP-LSI
Reference numeral 2 denotes an object arranged on the first layer.

Further, the through-via hole 91 is connected to the solder ball 11 via the first layer pattern 311 as a GND terminal of the chip-size package LSI 1.
And the fourth layer pattern 34 which is a GND layer, and the bypass capacitor 15 via a sixth layer pattern 361.

The through-via hole 92 is formed in the chip size package L through the first layer pattern 312.
The sixth ball pattern 3 of the bypass capacitor 15 is provided via the solder ball 12 serving as a power terminal of the SI1, the third layer pattern 33 serving as a power layer, and the sixth layer pattern 362.
It is connected to the terminal opposite to the terminal connected to 61.

On the other hand, with respect to the through-via hole 95, similarly to the through-via hole 91, the QFP-L
GND terminal of SI2 and fourth layer pattern 3 as GND layer
4 and the bypass capacitor 22 in the sixth layer pattern 3
63 and the through-via hole 96
Is the same as the QFP-L as in the case of the through-via hole 92.
The power supply terminal of SI2, the third layer pattern 33 as a power supply layer, and the bypass capacitor 22 are connected to a sixth layer pattern 364.
Connected through.

Further, the chip size package LSI
1 signal terminal 13 is connected to the second layer pattern 32 via the first layer pattern 313 and the partial VIA hole 93.
Via the first layer pattern 314 and a desired terminal of the QFP-LSI 2 via the first via pattern 94 located on the extension of the second layer pattern 32.

The signal terminals 14 and 15 of the chip size package LSI 1 are directly connected to desired terminals of the QFP-LSI 2 via the first layer pattern 314.

The QFP-LSI 24 is connected to an external circuit using a sixth layer pattern 365, and the QFP-LSI 2 is connected to an external circuit via the terminal 23 using a first layer pattern 315.

[0027]

The connection between a chip size package LSI using a conventional six-layer printed wiring board as shown in FIG. 8 and a QFP-LSI is realized by using an inexpensive four-layer printed wiring board. think of.

FIG. 9 shows a configuration using a four-layer printed wiring board.

In FIG. 9, the parts denoted by the same reference numerals as those in FIG. 8 are the same as those described above with reference to FIG.

Reference numeral 4 denotes a four-layer printed wiring board;
To 415, 42, 43, 441 to 444 denote patterns of the first to fourth layers having conductivity of the printed wiring board 4, respectively.

Reference numeral 401 denotes an electrical insulator for insulating the first layer patterns 411 to 415 provided on the printed wiring board 4 from the second layer pattern 42;
Reference numerals 2 and 403 denote electrical insulators that insulate between the second layer pattern 42 and the third layer pattern 43 and between the third layer pattern 43 and the fourth layer patterns 441 to 444, respectively.

Reference numerals 81, 82, 85, and 86 denote through-via holes provided in the printed wiring board 4, respectively.
Denotes a partial VIA hole provided in the printed wiring board 4 for connecting the first layer and the second layer.

The third layer pattern 43 is a power supply layer for supplying power to the chip size package LSI1 and the QFP-LSI2, and the fourth layer pattern 44 is a chip size package LSI1 and the QFP-LSI
This is a GND layer for setting reference potentials 2 and 24.

442, 443 and 444 are small patterns which are not in the GND potential and exist in the same layer as the fourth layer pattern 441.
5 and 22 and small patterns for wiring to the QFP-LSI 24.

The bypass capacitors 15, 22 and the QFP-LSI 24 are arranged in a fourth layer, and the chip size package LSI1 and the QFP-LSI
Reference numeral 2 denotes an object arranged on the first layer.

The through via hole 81 is formed in the chip size package L through the first layer pattern 411.
The solder ball 11, which is a GND terminal of SI1,
It is connected to the bypass capacitor 15 via a fourth layer pattern 441 having a D potential.

The through via hole 82 is formed in the chip size package L through the first layer pattern 412.
The terminal connected to the fourth layer pattern 441 of the bypass capacitor 15 via the solder ball 12 as the power terminal of the SI1, the third layer pattern 43 as the power layer, and the fourth layer pattern 442 Connected to the opposite terminal.

On the other hand, as for the through-via hole 85, similarly to the through-via hole 81, the QFP-L
The GND terminal of SI2, the fourth layer pattern 441 at GND potential, and the bypass capacitor 22 are connected to each other. The through VIA hole 86 is connected to the power supply terminal of the QFP-LSI 2 like the through VIA hole 82. The bypass capacitor 22 is connected to a terminal of the bypass capacitor 22 on a side opposite to the terminal connected to the fourth layer pattern 441 via a third layer pattern 43 as a layer and a small pattern 443 existing in the fourth layer. .

The chip size package LSI
1 signal terminal 13 is connected to the second layer pattern 42 via the first layer pattern 413 and the partial VIA hole 83.
Through the first layer pattern 414, and is connected to a desired terminal of the QFP-LSI 2 via the first layer pattern 414.

The signal terminals 14 and 15 of the chip size package LSI1 are directly connected to desired terminals of the QFP-LSI2 via the first layer pattern 414.

The QFP-LSI 2 is connected to the terminal 2
3 using the first layer pattern 415 through the QFP-
The LSI 24 is connected to an external circuit using the fourth layer pattern 444.

In the case of the above configuration, as apparent from FIG. 9, the pattern 441 for determining the GND potential of the fourth layer is used.
Are small patterns 442, 443, 444 other than the GND potential
It can be seen that the separation by the fourth layer pattern 444 is particularly large.

With the fourth layer pattern 444,
The impedance of the GND, which is the fourth layer pattern 441, rises, and an environment in which noise is easily generated is provided.

Further, the QFP-
In order to secure the connection between the LSI 24 and the fourth layer GND pattern 441, the QFP-L mounted on the fourth layer
The routing of the signal pattern 444 from the SI 24 is greatly restricted, and the through VIA for wiring in the second layer is provided.
The number of holes increases, and the power supply layer existing in the third layer is cut off by the penetrating VIA, thereby further increasing noise emission and deteriorating noise resistance.

In FIG. 9, the third layer is assigned to the power supply layer and the fourth layer is mainly assigned to the GND layer. However, the relationship between these layers is reversed, and the third layer is assigned to the GND layer and the fourth layer is assigned to the fourth layer. Is assigned to the power supply layer, since the QFP-LSI 24 still exists in the fourth layer governed by the power supply pattern, the wiring of the components is difficult, and the number of components that can be mounted on the fourth layer is reduced. The restrictions are the same.

[0046]

In view of the above-mentioned problems, a four-layer printed wiring board according to the present invention, in which a chip-size package LSI and a QFP-LSI coexist in the same layer, provides a wiring between the chip-size package LSI and the QFP-LSI. In the first layer, the second layer is provided with a pattern for wiring between the chip size package LSI and the QFP-LSI, the third layer is provided with a GND pattern, the fourth layer is provided with a power supply pattern, In other areas, the first layer and the fourth layer
A pattern for wiring signals in the layer, a power supply pattern in the second layer, and a GND pattern in the third layer are provided. In a region where wiring between the chip size package LSI and the QFP-LSI is performed, the first layer pattern and the This is a configuration using a partial VIA hole as the VIA hole connecting the two-layer pattern.

As a result, it is possible to provide a method for preventing an increase in the GND impedance and alleviating the restriction when the components are arranged on the fourth layer.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first invention of the present invention is a first LSI which is a package in which terminals of the LSI are arranged in a lattice pattern on the back surface of the package in a four-layer printed wiring board.
And a second LSI, which is a package in which terminals of the LSI are arranged in a line on four sides of a square package, in the first layer, the first LSI and the second LSI
As for the region where the wiring between I and I is performed, a first layer, a second layer as a signal wiring layer, a third layer as a GND layer, a fourth layer as a power supply layer, The second LSI
The first and fourth layers are divided into the signal wiring layer, the third layer as the GND layer, and the second layer as the power supply layer. Through which connects a fourth power supply layer in a region where wiring is performed between the first LSI and the second LSI, and a second power supply layer in a region not between the first LSI and the second LSI. VIA Hall
And a region for wiring between the first LSI and the second LSI;
A four-layer printed wiring board characterized in that the GND layer in a region other than between the SI and the second LSI is arranged on the same layer so that the GND layer is not divided. With such a configuration, when the ball pitch of the chip-size package LSI is narrow and a pattern cannot be drawn from the inner peripheral ball using only the first layer, the inner peripheral ball is formed using a partial VIA hole. In the case where connection is made to the second layer and wiring is performed using the second layer, it is possible to arrange and wire components on the fourth layer in a region not between the first LSI and the second LSI. Is what you do.

Further, in the second invention, there is provided a fourth power supply layer in a region where a wiring is provided between the first LSI and the second LSI and not between the first LSI and the second LSI. A four-layer printed wiring board in which the through-via hole connecting the power supply layer of the second layer in the area is arranged at the end of the printed wiring board, and even when the wiring passes through the area occupied by the second LSI, By arranging the through VIA holes connecting the two power supply layers at the end of the substrate, the restriction on the number of the through VIA holes can be reduced and the power supply impedance can be reduced.

Further, in the third invention, there is provided a power supply layer of a fourth layer in a region where wiring is performed between the first LSI and the second LSI, and not between the first LSI and the second LSI. A fourth layer having a component for electrically isolating the power supply layer of the region from the second power supply layer, and a power supply of the second layer in a region not between the first LSI and the second LSI of the power supply separation component A through via hole used for connection to a layer is formed between the first LSI and the second LSI.
A fourth power supply layer in a region where wiring is performed between LSIs, and a second power supply layer in a region not between the first LSI and the second LSI.
This is a four-layer printed wiring board configured so as to also serve as the through-via hole for connecting a power supply layer of the same layer.

With this configuration, for example, the first
A power supply used in a region where wiring between the first LSI and the second LSI is performed is a digital processing power supply, and the first LSI
In the case where the power supply in a region other than the area between the second LSI and the second LSI is a power supply for analog processing, in a conventional four-layer printed wiring board, the input / output terminals of an inductor, a regulator, and the like that separate these components are present in an inner layer. Through VIA to power supply layer
At least one hall was required for both input and output.

According to the third aspect of the present invention, components such as an inductor and a regulator are located in the fourth layer, and one terminal of this component is connected to the power supply pattern in the fourth layer. Only one through VIA hole is required before or after the component having the inductance component.
When the IA hole is used, the voltage drop due to the resistance component of the through VIA hole can be halved.

(First Embodiment) A four-layer printed wiring board according to an embodiment of the present invention will be described below in detail with reference to the drawings.

FIGS. 1 and 2 to 5 show the first embodiment of the present invention.
2A and 2B are a cross-sectional view of a four-layer printed wiring board and a perspective view of the first to fourth layers as viewed from the top of the first layer in the example of FIG.

In FIGS. 1 and 2 to 5,
8 and 9 have the same configuration as those in FIGS. 8 and 9 and will not be described in detail.

In FIGS. 1 and 2 to 5, 71,
Reference numerals 72, 73, 74, and 75 denote through-via holes provided in the printed wiring board 4, and reference numeral 521 denotes a pattern having a different potential from the second layer pattern 42 of the printed wiring board 4.
3 is a third layer pattern of the printed wiring board 4;
To 544 are fourth layer patterns of the printed wiring board 4.

The third layer pattern 53 is formed by the chip size package LSI1 and the QFP-LSI.
A GND pattern for setting reference potentials of 2, 24,
The fourth layer pattern 541 and the second layer pattern 5
21 is the chip size package LSI 1 and Q
This is a power supply pattern for supplying power to the FP-LSIs 2 and 24.

The through via hole 71 is formed in the chip size package L through the first layer pattern 411.
The solder ball 11 which is a GND terminal of SI1, the third-layer GND pattern 53, and the fourth-layer pattern 542
Is connected to the bypass capacitor 15.

The through via hole 72 is formed in the chip size package L through the first layer pattern 412.
The bypass capacitor 1 is connected to the solder ball 12 as a power supply terminal of the SI 1 and the fourth layer power supply pattern 541.
5 is connected to a terminal opposite to the terminal connected to the fourth layer pattern 542.

On the other hand, the through-via hole 73 also has the QFP-L
The GND terminal of SI2 is connected to the bypass capacitor 22 via a third layer pattern 53 and a fourth layer pattern 543 which are GND potentials. The through via hole 74 is similar to the through via hole 72. QF
The fourth terminal of the bypass capacitor 22 is connected via a power supply terminal of the P-LSI 2 and a fourth layer pattern 541 which is a power supply layer.
The terminal connected to the terminal opposite to the terminal connected to the layer pattern 543 is connected.

The through-via hole 75 is located below the QFP-LSI 2 and connects the fourth layer pattern 541 as a power supply pattern to the second layer pattern 521.

The QFP-LSI 24 is placed in a region where the chip size package LSI 1 and the QFP-LSI 2 are connected, that is, in the region of the fourth layer other than the region occupied by the first layer pattern 414 and the second layer pattern 42.

Further, the chip size package LSI
1 signal terminal 13 is connected to the second layer pattern 42 via the first layer pattern 413 and the partial VIA hole 83.
Through the first layer pattern 414, and is connected to a desired terminal of the QFP-LSI 2 via the first layer pattern 414.

The signal terminals 14 and 15 of the chip size package LSI 1 are directly connected to desired terminals of the QFP-LSI 2 via the first layer pattern 414.

The QFP-LSI 2 is connected to the terminal 2
3 using the first layer pattern 415 through the QFP-
The LSI 24 is connected to an external circuit using the fourth layer pattern 544.

In the first embodiment described above, FIGS.
As shown in FIG. 4, by switching the power supply pattern from the fourth layer pattern 541 to the second layer pattern 521, the third layer pattern 53 which is a GND pattern as shown in FIG.
Can be prevented from increasing the GND impedance.

Further, the arrangement of the QFP-LSI on the fourth layer, which was difficult with the conventional four-layer printed wiring board, is performed by changing the area where the chip size package LSI1 and the QFP-LSI2 are connected, that is, the first layer pattern 414, the fourth layer. By placing it in the area of the fourth layer other than the area occupied by the two-layer pattern 42,
The power supply of the QFP-LSI arranged in the fourth layer, the wiring to GND, and the signal wiring can coexist.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a region view of the four-layer printed wiring board according to the second embodiment of the present invention as viewed from above the first layer.

In FIG. 6, 1 is a chip size package LSI placed on the first layer, and 2 is a QF package placed on the first layer.
P-LSI, 24 is a QFP-LSI placed on the fourth layer,
101 is a first layer, a second layer is a signal pattern for connection between the chip size package LSI1 and the QFP-LSI2, a third layer is a GND pattern, and a fourth layer is a region used for a power supply pattern. The layer and the fourth layer are used as a signal pattern, the third layer is used as a GND pattern, and the second layer is used as a power supply pattern. A region 75 is provided in the power supply pattern existing in the fourth layer of the region 101 and a region used in the second layer of the region 102. This is a through VIA hole for connecting a power supply pattern to be formed.

Here, it is assumed that one or more reference numerals 75 exist on one or more sides around the four-layer printed wiring board.

In the first embodiment, the region 101 and the region 10
Via hole 75 for connecting two power supply patterns to each other
Is limited under the QFP-LSI 2, it is difficult to provide a sufficient number of through-via holes 75.

In the second embodiment, since it can be placed around the four-layer printed wiring board, the degree of freedom in providing the through-via hole 75 is increased. As a result, the fourth layer QFP-LSI 24 About power, G
Wiring to ND and signal wiring can coexist. (Third Embodiment) Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 7 shows a third embodiment of the present invention viewed from above the first layer.
FIG. 4 is a region diagram of a four-layer printed wiring board according to the example of FIG.

In FIG. 7, 1 is a chip size package LSI placed on the first layer, and 2 is a QF package placed on the first layer.
P-LSI, 24 is a QFP-LSI placed on the fourth layer,
101 is a first layer, a second layer is a signal pattern for connection between the chip size package LSI1 and the QFP-LSI2, a third layer is a GND pattern, and a fourth layer is a region used for a power supply pattern. The layer and the fourth layer are used as a signal pattern, the third layer is used as a GND pattern, the second layer is used as a power supply pattern, 103 is a first layer used as a signal pattern, and the second and fourth layers are used as a power supply pattern. A region where the third layer is used for the GND pattern, 75 is one or more through-via holes connecting the power supply pattern existing in the fourth layer of the region 103 and the power supply pattern existing in the second layer, and 6 is the region 101
Is a component having an inductance component that electrically separates the power supply pattern of FIG.

The area 13 is located at the boundary between the area 101 and the area 102. With such a configuration, the power supply can be separated between the region 101 and the region 102, and transmission of noise such as power supply ripple generated in the region 101 to the power supply in the region 102 can be prevented, or
The transmission of power supply noise generated in the area 101 to the area 102 can be prevented, and the wiring of the fourth layer QFP-LSI 24 to the power supply, GND, and signal wiring can coexist.

In the conventional four-layer printed wiring board, in order to separate the power supply, the power supply is temporarily transferred from the power supply pattern of the second or third layer to the first or fourth layer by using a through-via hole. Since the pattern is pulled out and connected to the power supply pattern of the second or third layer again using the through VIA hole via the component having the inductance component placed on the first or fourth layer, the through VIA hole is Necessary before and after parts with inductance components.

However, according to the third aspect of the present invention, the component having the inductance component is located on the fourth layer, and
Since one terminal of this component is connected to the power supply pattern of the fourth layer, only one through VIA hole is required before or after the component having the inductance component. When the same number of through VIA holes are used, The voltage drop due to the resistance component of the through-via hole can be halved.

In the above-described embodiment, a component having an inductance component is used as a component for separating a power supply. However, a component or a component group for converting a power supply voltage may be similarly applied to the QFP-LSI 24 of the fourth layer. Power supply, GND
Wiring and signal wiring can coexist.

[0078]

According to the present invention, in a four-layer printed wiring board, a chip size package LSI is provided on a first layer,
When the QFP-LSI is mounted and wiring between them is required, the ball pitch of the first-layer chip size package LSI is narrow, and it is not possible to draw a pattern from the inner peripheral ball using only the first layer. In this case, the inner peripheral ball is connected to the second layer using the partial VIA hole,
In the case of wiring using layers, components can be arranged and wired on the fourth layer using a four-layer printed wiring board, and components can be arranged on the front and back of the board using a conventional six-layer printed wiring board. The cost of the printed wiring board can be reduced as compared with the case where it has been performed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a four-layer printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a top view of a first layer of FIG. 1;

FIG. 3 is a top view of a second layer in FIG. 1;

FIG. 4 is a top view of a third layer of FIG. 1;

FIG. 5 is a top view of a fourth layer in FIG. 1;

FIG. 6 is a top perspective view of a four-layer printed wiring board according to a second embodiment of the present invention.

FIG. 7 is a top perspective view of a four-layer printed wiring board according to a third embodiment of the present invention.

FIG. 8 is a sectional view of a conventional six-layer printed wiring board.

FIG. 9 is a sectional view of a conventional four-layer printed wiring board.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 chip size package LSI 2, 24 QFP-LSI 11 GND terminal ball 12 power supply terminal ball 13, 14, 15 signal terminal ball 16, 22 bypass capacitor 21, 23 terminal 4 four-layer printed wiring board 401, 402, 403 insulating layer 411 GND terminal land 412 Power terminal land 413 Signal terminal land 414 Signal wiring 415 Chip size of QFP-LSI arranged on first layer Wiring to other than package LSI 42 QFP-LSI chip arranged on second layer Wiring to size package LSI 521 Power supply layer 53 GND layer 541 Power supply layer 542, 643 Land for 544 544 Signal wiring 101 arranged in fourth layer 101 First and second layers are signal layers, third layer is GND layer,
The fourth layer is a region of a power supply layer 102 The first layer, the fourth layer is a signal layer, the third layer is a GND layer,
The second layer is a region of a power layer 103. The first layer is a signal layer, the second and fourth layers are regions of a power layer, and the third layer is a region of a GND layer. 6 Power separation components 71, 72, 73, 74, 75, 83 , 84 VIA Hall

Claims (3)

[Claims] 1. A first LSI having a plurality of terminals on a back surface of a package on a first layer of a four-layer printed wiring board, and a second LSI having a plurality of terminals around a package. In a region where wiring between the first LSI and the second LSI is performed, a layer configuration in which a first layer and a second layer are signal wiring layers, a third layer is a GND layer, and a fourth layer is a power supply layer. A layer having a first layer and a fourth layer as signal wiring layers, a third layer as a GND layer, and a second layer as a power supply layer, for a region and a region not between the first LSI and the second LSI. A fourth power supply layer in a region where wiring is performed between the first LSI and the second LSI, and a fourth power supply layer in a region not between the first LSI and the second LSI. A penetrating via hole connecting the two power supply layers is arranged in a region occupied by the second LSI, and A region for wiring between an LSI and the second LSI, and a first LSI and a second LSI
By arranging the GND layer in an area that is not between them on the same layer,
A four-layer printed wiring board characterized in that the ND layer is not divided. 2. A power supply layer of a fourth layer in a region where wiring is performed between a first LSI and a second LSI, and a power supply of a second layer in a region not between the first LSI and the second LSI. 2. The four-layer printed wiring board according to claim 1, wherein the through-via holes connecting the layers are arranged at the ends of the printed wiring board. 3. A power supply layer of a fourth layer in a region where wiring is performed between the first LSI and the second LSI, and a power supply of a second layer in a region not between the first LSI and the second LSI. A fourth layer having a component for electrically separating a layer from the first layer, and a through hole used for connecting a power supply separating component to a second power supply layer in a region not between the first LSI and the second LSI; A VIA hole is formed in a fourth power supply layer in a region where wiring is performed between the first LSI and the second LSI, and the first LSI and the second LSI
2. The four-layer printed wiring board according to claim 1, wherein the via also serves as the through-via hole for connecting to a second power supply layer in a region not between the SIs.