JPH0983141A - Method of manufacturing ceramic multi-layered substrate - Google Patents

Method of manufacturing ceramic multi-layered substrate

Info

Publication number
JPH0983141A
JPH0983141A JP7230899A JP23089995A JPH0983141A JP H0983141 A JPH0983141 A JP H0983141A JP 7230899 A JP7230899 A JP 7230899A JP 23089995 A JP23089995 A JP 23089995A JP H0983141 A JPH0983141 A JP H0983141A
Authority
JP
Japan
Prior art keywords
ceramic
sheet
alumina
via conductor
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7230899A
Other languages
Japanese (ja)
Inventor
Osamu Shiraishi
理 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7230899A priority Critical patent/JPH0983141A/en
Publication of JPH0983141A publication Critical patent/JPH0983141A/en
Pending legal-status Critical Current

Links

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Abstract

PROBLEM TO BE SOLVED: To simply form a protruded electrode of a ceramic multi-layered substrate in which shorticircuiting is prevented even when terminals are narrowed in pitches thereof and which is unlikely to be affected by thermal distortion in a method of manufacturing the ceramic multi-layered substrate suitable for a CSP(chip size package). SOLUTION: Alumina sheets 1, 12 are disposed on the upper and lower surfaces of a laminated non-calcined glass ceramic sheet 2 for restricting contraction thereof upon calcination. An opening 13 is formed in the alumina sheet 12 at a position of a via conductor 3. With calcination in this state, the glass ceramic sheet 2 is contracted in the height direction while the via conductor 3 having the opening 13 is not contracted but protruded. Once the alumina sheet 12 is removed, a ceramic substrate 4 having a protruded electrode 14 is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子機器に使用される
セラミック多層基板の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a ceramic multilayer substrate used in electronic equipment.

【0002】[0002]

【従来の技術】近年、Siチップ内でのサブミクロン化
技術は急速に進み、ICの高集積度化、高密度化の進展
は目を見張るものがある。しかし、これに伴ってSiチ
ップの大型化や多電極化が進み、ICパッケージの大型
化は避けられなくなってきている。このため、端子リー
ドの狭ピッチ化も急速に進んできているものの、ICの
実装効率(ICチップ面積/ICパッケージ面積)は5
0%以下と低く、これが実装効率を下げる一因となって
いる。
2. Description of the Related Art In recent years, submicron technology in Si chips has been rapidly advanced, and progress in higher integration and higher density of ICs has been remarkable. However, along with this, the size of the Si chip and the increase in the number of electrodes have advanced, and the size of the IC package has become unavoidable. Therefore, although the pitch of the terminal leads has been rapidly narrowed down, the mounting efficiency of the IC (IC chip area / IC package area) is 5
It is as low as 0% or less, which is one of the causes for lowering the mounting efficiency.

【0003】そこでチップサイズパッケージ(以下CS
Pと略す)と呼ばれる新しい半導体パッケージが開発さ
れ、電子回路のデジタル化に伴って、セラミック多層基
板の利用が注目されている。図3の断面図は、セラミッ
ク多層基板を利用した代表的なCSPの構造を示してい
る。
Therefore, a chip size package (hereinafter referred to as CS
A new semiconductor package called P) has been developed, and with the digitization of electronic circuits, attention has been paid to the use of ceramic multilayer substrates. The cross-sectional view of FIG. 3 shows a typical CSP structure using a ceramic multilayer substrate.

【0004】図において、5は半導体素子であり、その
アルミ電極6にはバンプ10を形成している。また4は
ガラスセラミックシートを積層して焼結したセラミック
多層基板であり、各層間の電気的導通はビア導体3と内
部導体11で得ている。CSPに際しては、セラミック
多層基板4の基板電極9上に接着用の半田10を塗布
し、半導体素子5のバンプ10を位置合わせして載置し
て両者を固定した後、間隙を樹脂8で封止している。
In the figure, numeral 5 is a semiconductor element, and a bump 10 is formed on an aluminum electrode 6 thereof. Reference numeral 4 denotes a ceramic multilayer substrate obtained by laminating and sintering glass ceramic sheets, and electrical conduction between layers is obtained by the via conductor 3 and the internal conductor 11. At the time of CSP, solder 10 for adhesion is applied on the substrate electrodes 9 of the ceramic multilayer substrate 4, the bumps 10 of the semiconductor element 5 are aligned and placed, and both are fixed, and then the gap is sealed with a resin 8. It has stopped.

【0005】[0005]

【発明が解決しようとする課題】しかしながら上記従来
のように、バンプ電極を形成して半導体素子を実装する
場合、より小径のバンプを形成していくことには限界が
あり困難となる。このため端子の狭ピッチ化にバンプの
小径化が対応できなくなり、半田等の接着剤の広がりに
よって、端子間のショートが多発することになる。
However, when the bump electrodes are formed and the semiconductor element is mounted as in the conventional case, it is difficult to form bumps having a smaller diameter because there is a limit. For this reason, it becomes impossible to reduce the diameter of the bumps to the narrow pitch of the terminals, and short-circuiting between terminals frequently occurs due to the spread of the adhesive such as solder.

【0006】またバンプを高く形成することが困難であ
るために、半導体素子とセラミック多層基板の距離を大
きくできず、両者の熱膨張係数の差による歪を充分に吸
収しきれない問題もある。
Further, since it is difficult to form the bumps at a high height, the distance between the semiconductor element and the ceramic multilayer substrate cannot be increased, and there is a problem that the strain due to the difference in thermal expansion coefficient between the two cannot be fully absorbed.

【0007】そこで本発明は、無収縮基板を利用するこ
とによって、セラミック多層基板の焼成と同時に、端子
の狭ピッチ化や熱歪にも充分対応できる突起電極を形成
することのできる、セラミック多層基板の製造方法を提
供する。
In view of the above, the present invention utilizes a non-shrinkable substrate, and at the same time as firing the ceramic multi-layer substrate, it is possible to form a protruding electrode which can sufficiently cope with a narrow pitch of terminals and thermal strain. A method for manufacturing the same is provided.

【0008】[0008]

【課題を解決するための手段】上記課題を解決するため
に、本発明のセラミック多層基板の製造方法は、積層し
た未焼成のセラミックシートの上面に、前記積層したセ
ラミックシート間を貫くビア導体の位置に、突起電極を
形成すべき大きさの開孔を有するとともに、前記突起電
極の高さに応じた厚さを有する収縮抑制シートを載置し
てから焼成するようにしたものである。
In order to solve the above-mentioned problems, a method for manufacturing a ceramic multilayer substrate according to the present invention comprises a via conductor penetrating between the laminated ceramic sheets on the upper surface of the laminated unfired ceramic sheets. An opening having a size for forming a protruding electrode is provided at a position, and a shrinkage suppression sheet having a thickness corresponding to the height of the protruding electrode is placed and then fired.

【0009】[0009]

【作用】上記方法によれば、ビア導体は焼成時に発生す
る収縮ストレスを受けることなく焼き上がる。したがっ
て収縮抑制シートを除去すると、そのシートの開孔に応
じた径と高さの突起電極が現れる。
According to the above method, the via conductor is baked without receiving the contraction stress generated during baking. Therefore, when the shrinkage suppression sheet is removed, a protruding electrode having a diameter and height corresponding to the opening of the sheet appears.

【0010】[0010]

【実施例】以下、本発明の実施例について、図面を参照
しながら説明する。図1は一実施例のセラミック多層基
板の製造方法における各工程を示す断面図である。図1
(a)において、1,12はアルミナシートであり、積
層した未焼成のガラスセラミックシート2の上面及び下
面に配置することで、焼成時にガラスセラミックシート
2の収縮を制御する。アルミナシート12には、積層し
たガラスセラミックシート2間の導通を得るビア導体3
の位置に、NCパンチでビア導体3と同径の開孔13を
形成している。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing each step in a method for manufacturing a ceramic multilayer substrate according to an embodiment. FIG.
In (a), 1 and 12 are alumina sheets, which are arranged on the upper surface and the lower surface of the laminated unfired glass ceramic sheets 2 to control the shrinkage of the glass ceramic sheets 2 during firing. Via conductors 3 are provided on the alumina sheet 12 to provide conduction between the laminated glass ceramic sheets 2.
An opening 13 having the same diameter as that of the via conductor 3 is formed at the position of with an NC punch.

【0011】この状態で焼成を行うと、図1(b)に示
すように、アルミナシートは焼結しないが、内部のガラ
スセラミックシート2は焼結する。このときガラスセラ
ミックシート2は、アルミナシート1,12によりX,
Y方向、すなわち平面方向の収縮が抑制され、Z方向す
なわち高さ方向は抑制されず、約55〜60%に収縮す
る。
When firing is performed in this state, as shown in FIG. 1B, the alumina sheet is not sintered, but the glass ceramic sheet 2 inside is sintered. At this time, the glass ceramic sheet 2 is X
The shrinkage in the Y direction, that is, the plane direction is suppressed, and the Z direction, that is, the height direction is not suppressed, and the shrinkage is about 55 to 60%.

【0012】このためアルミナシート12に形成した開
孔13の部分は、収縮が抑制されないので、焼成と同時
にビア導体3が突起電極として盛り上がってくる。その
後アルミナシート1,12を除去すると、図1(c)に
示すように、突起電極14を有するセラミック多層基板
4が得られる。
Therefore, the opening 13 formed in the alumina sheet 12 is not restrained from shrinking, so that the via conductor 3 rises as a protruding electrode at the same time as firing. Then, by removing the alumina sheets 1 and 12, the ceramic multilayer substrate 4 having the protruding electrodes 14 is obtained as shown in FIG.

【0013】上記のようにして得られたセラミック多層
基板を用いてCSPを行うに際しては、図2に示すよう
に、半導体素子5のアルミ電極6に接着剤となる半田7
を塗布した後、セラミック多層基板4に載置してから樹
脂8で封止する。
When performing CSP using the ceramic multi-layer substrate obtained as described above, as shown in FIG. 2, the solder 7 serving as an adhesive is attached to the aluminum electrode 6 of the semiconductor element 5.
After being applied, it is placed on the ceramic multilayer substrate 4 and then sealed with the resin 8.

【0014】ここで、開孔13の大きさやアルミナシー
ト12の厚さを調整することにより、突起電極の径や高
さを制御することができる。例えば開孔13をビア導体
3の径より小さくすれば、より小径の突起電極14を得
ることができ、端子間の狭ピッチ化にも対応できる。ま
たアルミナシート12を複数枚重ねて用いると、突起電
極13の高さを高くすることができ、半導体素子5とセ
ラミック多層基板4の距離を大きくすることができる。
このため線膨張係数の差の影響を受けにくく、また断線
しにくくできる。
Here, by adjusting the size of the opening 13 and the thickness of the alumina sheet 12, the diameter and height of the protruding electrode can be controlled. For example, if the diameter of the opening 13 is smaller than the diameter of the via conductor 3, it is possible to obtain the protruding electrode 14 having a smaller diameter, and it is possible to cope with a narrower pitch between terminals. When a plurality of alumina sheets 12 are stacked and used, the height of the bump electrode 13 can be increased and the distance between the semiconductor element 5 and the ceramic multilayer substrate 4 can be increased.
Therefore, it is difficult to be affected by the difference in the linear expansion coefficient, and it is possible to prevent the disconnection.

【0015】なお上記実施例においては、焼成時に、ビ
ア導体3がアルミナシート12の上面から突出してしま
うと、所望の形状の突起電極14が得られなくなる。こ
のためアルミナシート12の厚さは、焼成時に形成され
る突起電極14の高さよりも高くしなければならない。
また開孔13を小さくするにしたがって、形成される突
起電極14も高くなるので、この点も考慮してアルミナ
シートの厚さを決定しなければならない。
In the above embodiment, if the via conductor 3 projects from the upper surface of the alumina sheet 12 during firing, the projection electrode 14 having a desired shape cannot be obtained. Therefore, the thickness of the alumina sheet 12 must be higher than the height of the bump electrodes 14 formed during firing.
Further, as the size of the opening 13 becomes smaller, the formed protruding electrode 14 also becomes higher. Therefore, the thickness of the alumina sheet must be determined in consideration of this point as well.

【0016】[0016]

【発明の効果】以上のように本発明によれば、CSPに
適用して好適なセラミック多層基板を得ることができ、
特に、狭ピッチ化してもショートがなく、また熱歪の影
響も受けにくいセラミック多層基板の突起電極を、焼成
と同時に簡単に形成することができる。
As described above, according to the present invention, it is possible to obtain a suitable ceramic multilayer substrate by applying it to CSP,
In particular, it is possible to easily form the protruding electrodes of the ceramic multi-layer substrate which are not short-circuited even if the pitch is narrowed and are not easily affected by thermal strain, simultaneously with firing.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のセラミック多層基板の製造
方法における各工程を示す断面図
FIG. 1 is a sectional view showing each step in a method for manufacturing a ceramic multilayer substrate according to an embodiment of the present invention.

【図2】同方法により得たセラミック多層基板を利用し
たCSPの断面図
FIG. 2 is a sectional view of a CSP using a ceramic multilayer substrate obtained by the same method.

【図3】従来のCSPを示す断面図FIG. 3 is a sectional view showing a conventional CSP.

【符号の説明】[Explanation of symbols]

1,12 アルミナシート 2 ガラスセラミックシート 3 ビア導体 4 セラミック多層基板 5 半導体素子 6 アルミ電極 7 半田 8 樹脂 9 基板電極 10 バンプ 11 内部導体 13 開孔 14 突起電極 1, 12 Alumina Sheet 2 Glass Ceramic Sheet 3 Via Conductor 4 Ceramic Multilayer Substrate 5 Semiconductor Element 6 Aluminum Electrode 7 Solder 8 Resin 9 Board Electrode 10 Bump 11 Internal Conductor 13 Open Hole 14 Projection Electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】積層した未焼成のセラミックシートの上面
に、前記積層したセラミックシート間を貫くビア導体の
位置に、突起電極を形成すべき大きさの開孔を有すると
ともに、前記突起電極の高さに応じた厚さを有する収縮
抑制シートを載置してから焼成するようにしたセラミッ
ク多層基板の製造方法。
1. An upper surface of a laminated unfired ceramic sheet has an opening of a size for forming a protruding electrode at a position of a via conductor penetrating between the laminated ceramic sheets, and a height of the protruding electrode is increased. A method for manufacturing a ceramic multi-layer substrate in which a shrinkage suppression sheet having a thickness according to the thickness is placed and then fired.
JP7230899A 1995-09-08 1995-09-08 Method of manufacturing ceramic multi-layered substrate Pending JPH0983141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7230899A JPH0983141A (en) 1995-09-08 1995-09-08 Method of manufacturing ceramic multi-layered substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7230899A JPH0983141A (en) 1995-09-08 1995-09-08 Method of manufacturing ceramic multi-layered substrate

Publications (1)

Publication Number Publication Date
JPH0983141A true JPH0983141A (en) 1997-03-28

Family

ID=16915049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7230899A Pending JPH0983141A (en) 1995-09-08 1995-09-08 Method of manufacturing ceramic multi-layered substrate

Country Status (1)

Country Link
JP (1) JPH0983141A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060108908A (en) * 2005-04-13 2006-10-18 삼성전기주식회사 Method of manufacturing layer-built type ceramic substrate
JP2007324420A (en) * 2006-06-01 2007-12-13 Tdk Corp Ceramic substrate and composite wiring board, and manufacturing method thereof
JP2007324419A (en) * 2006-06-01 2007-12-13 Tdk Corp Ceramic substrate and composite wiring board, and manufacturing method thereof
JP2008047613A (en) * 2006-08-11 2008-02-28 Jatco Ltd Method for forming fixing part of surface mounting component to laminated ceramic substrate, method for fixing surface mounting component to fixing part, and laminated ceramic substrate used for these
US7463475B2 (en) 2005-07-27 2008-12-09 Murata Manufacturing Co., Ltd. Multilayer electronic component, electronic device, and method for manufacturing multilayer electronic component
US7807499B2 (en) 2004-09-29 2010-10-05 Murata Manufacturing Co., Ltd. Stacked module and manufacturing method thereof
US7903426B2 (en) 2005-10-26 2011-03-08 Murata Manufacturing Co., Ltd. Multilayer electronic component, electronic device, and method for producing multilayer electronic component
US8232481B2 (en) 2006-06-15 2012-07-31 Murata Manufacturing Co., Ltd. Wiring board with columnar conductor and method of making same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7807499B2 (en) 2004-09-29 2010-10-05 Murata Manufacturing Co., Ltd. Stacked module and manufacturing method thereof
KR20060108908A (en) * 2005-04-13 2006-10-18 삼성전기주식회사 Method of manufacturing layer-built type ceramic substrate
US7463475B2 (en) 2005-07-27 2008-12-09 Murata Manufacturing Co., Ltd. Multilayer electronic component, electronic device, and method for manufacturing multilayer electronic component
US7903426B2 (en) 2005-10-26 2011-03-08 Murata Manufacturing Co., Ltd. Multilayer electronic component, electronic device, and method for producing multilayer electronic component
JP2007324420A (en) * 2006-06-01 2007-12-13 Tdk Corp Ceramic substrate and composite wiring board, and manufacturing method thereof
JP2007324419A (en) * 2006-06-01 2007-12-13 Tdk Corp Ceramic substrate and composite wiring board, and manufacturing method thereof
JP4697600B2 (en) * 2006-06-01 2011-06-08 Tdk株式会社 Manufacturing method of composite wiring board
JP4706929B2 (en) * 2006-06-01 2011-06-22 Tdk株式会社 Composite wiring board and manufacturing method thereof
US8232481B2 (en) 2006-06-15 2012-07-31 Murata Manufacturing Co., Ltd. Wiring board with columnar conductor and method of making same
JP2008047613A (en) * 2006-08-11 2008-02-28 Jatco Ltd Method for forming fixing part of surface mounting component to laminated ceramic substrate, method for fixing surface mounting component to fixing part, and laminated ceramic substrate used for these

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