JPH0238969B2 - - Google Patents

Info

Publication number
JPH0238969B2
JPH0238969B2 JP58049889A JP4988983A JPH0238969B2 JP H0238969 B2 JPH0238969 B2 JP H0238969B2 JP 58049889 A JP58049889 A JP 58049889A JP 4988983 A JP4988983 A JP 4988983A JP H0238969 B2 JPH0238969 B2 JP H0238969B2
Authority
JP
Japan
Prior art keywords
stage
storage device
signal
regular
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58049889A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59177796A (ja
Inventor
Mitsuki Fukuzumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp filed Critical Fuji Electric Co Ltd
Priority to JP58049889A priority Critical patent/JPS59177796A/ja
Publication of JPS59177796A publication Critical patent/JPS59177796A/ja
Publication of JPH0238969B2 publication Critical patent/JPH0238969B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
JP58049889A 1983-03-25 1983-03-25 記憶装置の二重化制御方式 Granted JPS59177796A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58049889A JPS59177796A (ja) 1983-03-25 1983-03-25 記憶装置の二重化制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58049889A JPS59177796A (ja) 1983-03-25 1983-03-25 記憶装置の二重化制御方式

Publications (2)

Publication Number Publication Date
JPS59177796A JPS59177796A (ja) 1984-10-08
JPH0238969B2 true JPH0238969B2 (enrdf_load_stackoverflow) 1990-09-03

Family

ID=12843596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58049889A Granted JPS59177796A (ja) 1983-03-25 1983-03-25 記憶装置の二重化制御方式

Country Status (1)

Country Link
JP (1) JPS59177796A (enrdf_load_stackoverflow)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61160165A (ja) * 1984-12-29 1986-07-19 Fuji Facom Corp 記憶装置の二重化状態保持方式
JPS61243548A (ja) * 1985-04-22 1986-10-29 Nec Corp デ−タ記憶装置
JPS61251949A (ja) * 1985-04-30 1986-11-08 Nec Corp デ−タ記憶装置
JPS62222348A (ja) * 1986-03-25 1987-09-30 Fuji Electric Co Ltd 演算ユニツトの二重化方式
JPS6472248A (en) * 1987-09-11 1989-03-17 Nec Corp Memory device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5850372B2 (ja) * 1976-03-18 1983-11-10 日本電気株式会社 デ−タ集配信処理システム
JPS5584099A (en) * 1978-12-20 1980-06-24 Fujitsu Ltd Memory device
JPS55119761A (en) * 1979-03-10 1980-09-13 Fuji Electric Co Ltd Memory control unit

Also Published As

Publication number Publication date
JPS59177796A (ja) 1984-10-08

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