JPS6472248A - Memory device - Google Patents

Memory device

Info

Publication number
JPS6472248A
JPS6472248A JP62228985A JP22898587A JPS6472248A JP S6472248 A JPS6472248 A JP S6472248A JP 62228985 A JP62228985 A JP 62228985A JP 22898587 A JP22898587 A JP 22898587A JP S6472248 A JPS6472248 A JP S6472248A
Authority
JP
Japan
Prior art keywords
memory
acknowledge
answer
memory device
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62228985A
Other languages
Japanese (ja)
Inventor
Susumu Yoshino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62228985A priority Critical patent/JPS6472248A/en
Publication of JPS6472248A publication Critical patent/JPS6472248A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To facilitate the duplex structure of a memory device by operating, hereafter, a memory module received an instruction from a host device for queuing to perform writing jobs to the write instructions given from other devices but has no answer of acknowledge and has no reading job nor answer of acknowledge to the read instructions. CONSTITUTION:A memory device 2 consists of plural memory modules 5-7. In this case, the number of modules has no limitation. A memory module that received an instruction from a host device 3 for queuing performs hereafter the writing jobs but has no answer of acknowledge to the write instructions given from other devices. While said module has no writing job nor answer of acknowledge to the read instructions. In such a constitution, a memory can be easily duplicated with the small hardware quantity. Then a memory device with high reliability is obtained.
JP62228985A 1987-09-11 1987-09-11 Memory device Pending JPS6472248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62228985A JPS6472248A (en) 1987-09-11 1987-09-11 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62228985A JPS6472248A (en) 1987-09-11 1987-09-11 Memory device

Publications (1)

Publication Number Publication Date
JPS6472248A true JPS6472248A (en) 1989-03-17

Family

ID=16884962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62228985A Pending JPS6472248A (en) 1987-09-11 1987-09-11 Memory device

Country Status (1)

Country Link
JP (1) JPS6472248A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59177796A (en) * 1983-03-25 1984-10-08 Fuji Electric Co Ltd Duplication control system of memory
JPS6019257A (en) * 1983-07-12 1985-01-31 Nec Corp Control circuit for memory multiplex mode

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59177796A (en) * 1983-03-25 1984-10-08 Fuji Electric Co Ltd Duplication control system of memory
JPS6019257A (en) * 1983-07-12 1985-01-31 Nec Corp Control circuit for memory multiplex mode

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