JPS59177796A - Duplication control system of memory - Google Patents

Abstract

PURPOSE:To continue normal operation changing a normal memory to common use so for abnormality is not of the same address by not making cutting off from a system of common use side when the abnormality is detected in common use side, but by switching the common use/standby that switches standby side to the common use side and vice versa. CONSTITUTION:An address decode section 24 outputs a device select signal 18(SEL) to make the reading or writing of data of a memory 11 only when the memory 11 is accessed from a master device through a system bus 9. When there is abnormality in write data and read data to the memory 1, an error detecting section 2 outputs an error detection signal 3 (ERR) to a duplication control section 14. When the flip flop of the memory 11 is reset, a signal 21' (ACK) disappears in the memory 11' of the standby side, flip flop 15' is set to become the common use side. By setting of the flip flop 15' of the memory 11' which has been in the standby side, the signal 21(ACK) of the memory 11 which so far been in the common use side becomes effective.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a duplex control system for storage devices, and more particularly, to a duplex control system for storage devices in an information processing apparatus.

[Prior art and its problems]

Generally, when duplicating storage devices, there are the following methods. That is, one of the duplicated storage devices is set as the regular side and the other as the standby side, and when convolution is performed, they are operated simultaneously, the same content is written to the same location, and when read, only the data on the regular side is output. If an error occurs when reading from the regular side, the regular side is disconnected, and the other storage device that was on standby is switched to the regular side and immediately outputs correct data.

FIG. 1 and FIG. 2 illustrate a duplex control force formula for a storage device according to the prior art.

FIG. 1 is a block diagram of an example of a system in which a common dual-control unit is provided between two storage devices.

In the figure, 1 and 1' are storage units, 2 and 2' are error detection circuits, 6 and 6' are error detection signals, 4 and 4' are address inputs, 5 and 5' are write data, and 6 and 6' are Read data, 7 and 7' are duplex control gate signals, 8 is a common duplex control section, 9 is a system bus, and 10 and 10' are gates. The storage section 1' side functions as a standby side. error detection circuit 2,
2' checks the crowd cutter for the storage units 1 and 1', respectively, and when an abnormality is detected, sends an error detection signal 5 and 6'.
Then, the duplication control section 8 provided in common to the storage sections 1 and 1' is notified.

When operating with the storage unit 1 side as the regular side and the side 1' as the standby side, the duplex control unit 8 outputs only the duplex control color code 7, makes the game) 10 conductive, System bus 9 with the bladder output data output from storage unit 1 as valid.
However, the error detection circuit 2 of the storage unit 1 on the regular side
detects an error and the error detection signal 6 is input, the output of the duplex control unit 14 is stopped, the gate 10 is closed, and the output of the storage unit 1, which has been on the regular side until now, is stopped. and outputs the duplex control gate signal 7' instead.
The gate 10' is made conductive so that the output of the memory section 1' is made valid and sent to the system bus 9, that is, the memory section 1' is switched from the standby side to the regular side. The storage device that was previously the regular user has not been disconnected from the system.

The structure of the storage device is a single-layered structure with only the storage section 1'.

FIG. 2 shows a system in which the duplication control section (8) in FIG. 1 is provided separately for each storage device.

In FIG. 2, the reference numerals indicate the same as in the first. Note that i3, 13' is 21 provided corresponding to the storage units 1, 1'.
12 is a signal line for exchanging control information (regular use, standby status, presence or absence of errors, etc.) between the duplication control units 13 and 13', and 11 and 11' are storage units, respectively. 1, 1' and a duplication control section 16.degree. 13'.

In the case of the system shown in FIG. 2, when an error is detected in the read data in the storage device 11 on the regular side, the error detection circuit 2 sends an error detection signal 6 to the duplication control device 16, similarly to the system shown in FIG. This duplexing control device 13 stops outputting the duplexing control gate signal 7, closes the gate 10, stops outputting the storage device 1 which has been used regularly, and waits for error detection information via the signal line 12. When the redundancy control device 16' receives the error detection information, the redundancy control device 16' transfers the error detection information to the standby storage device 11'.
If it has not received the error detection signal 3', it outputs the redundant control signal 'r' fs number 7', opens the gate 10', and sends the read data from the standby storage device 1' to the system bus 9. Do it like this.

In this way, the standby 1tl becomes valid and the regular side is disconnected.

When performing the above-mentioned control, the above-mentioned conventional technology has the following problems.

(1) The storage device in which the error occurred is mainly disconnected from the system, and the disconnected storage device cannot be restarted.

(2) A common control unit for monitoring and controlling the status of each category is required for the two duplicated storage devices (Figure 1).

(3) If the previous item (2) is improved and a common control unit is not provided, but duplex control units are provided separately for two storage devices (Figure 2), mutual communication between each duplex control unit Exchanging control information generally requires multiple dedicated lines and complex means for controlling the transfer of the information to be exchanged.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the above-mentioned problems in the prior art in a storage device duplication control system, and to perform more reliable duplication control of a storage device by a simple means.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 6 is a diagram showing the configuration of an embodiment of the present invention.

In the figures, reference numbers refer to the same ones as in FIGS. 1 and 2.

Note that 11 and 11' in FIG. 3 are storage devices that are switched to the regular side and the standby side, respectively, and
14.14' is a duplication control unit, 15.15' is a flip-flop, 16.16' is an AND gate, 17. i7
'is device select i issue (SEX,), 19.19
'is the output enable number (RUN), 20.20' is the first run' setting switch, which operates mutually exclusively, 21
．． 21' is duplex control (ACK), 22, 22
' is an inversion circuit, and 24 and 24 ' are address decoding sections.

As is clear from the figure, the storage devices 11 and 11' have the same configuration, and the bottom portions of the storage device 11' and signals corresponding to the bottom portions and signals of the storage device 11 are denoted by the same reference numerals. I will ask and show you.

The operation of the storage device 11 will be explained.

When the storage device 11 is accessed from the master device via the system bus 9, the address decoding unit 24 outputs device selenium (R No. 18 (SEL)) and accesses the data in the storage device 11. , or enable writing. When there is an abnormality in the 1-input data or the bladder output data for the storage device 1, the error detection section 2 outputs an error detection signal 3 (ERR) to the duplication control section 14.

10 is an output drive node ((AND gate), the flip-flop 15 is set and its output enable is 100 (RUN) or 11", and the device select signal 18 (SEL) is '1'. ”, the AND gate 16 outputs 1, and the output “1” causes the output driver (10) to operate and output the read data sent from the storage unit 1 via the line 6 to the system bus 9. Alternatively, a response signal to the master device can be output to the system bus 9. At this time, the storage device 11 is on the regular side.

The duplexing control unit 14 is configured as follows: Engineering 2 - Detection color code 3 (ERR) Output enable signal 19 (##) Signal indicating the state of the initial setting switch 9 (MST) Duplexing control signal 21 (ACK) Device select signal 1B (SEL ) Group 7 e) As an input condition, duplex control is performed by setting and resetting the flip-flop 15 based on a state transition diagram (FIG. 4) to be described later. Furthermore, flip 70
The plug 15 is reset when the system is started up. The initial setting switch 20 is set exclusively with the initial setting switch 20' of the paired storage device 11', and determines the priority order for acquiring regular use rights for the duplex control unit 14, 14' at the time of system startup.

Line 26 is connected to NAND gate 17. of storage device 11.11'.
17' are wired-OR connected, and the output enable signal 19 (RUN) output from the flip-flop 15.15' is ORed. ' is received as a duplication control signal 21.21' (ACK).

The dual control units 14.14' provided in the storage devices 11.11' respectively output the output signal 19.19' (RUN) of the flip-flop 15.15' and the signal 21.2.
1' (ACK) can be used to recognize mutual states.

Further, the duplication control signals 21 and 21' (ACK) become valid when the storage devices 11 and 11' are accessed from the mask device and the device select signal h18°18' (SEL) becomes valid. It is only during the period when

That is, the main signal 21.21' (ACK) can be used in a time-sharing manner by the duplexing devices of the digit group that perform duplexing control.

Next, various signals (ERR, ACK, R
U.N.

The control state, ie, how the flip 70 knob 15 is controlled in accordance with the input conditions of (SEL, MST, etc.) will be explained.

The inputs to the duplication control unit 14 are the above five types,
Its output is SET,R for flip-flop 15
This is the ESET Hakugo.

The duplication control unit 14 uses a plurality of control stages and appropriately controls the flip-flop 15 to perform duplication! Do IJ XI. The fIiil kl stage is similar to the stage of type 7. That is, Sl...
Non-selection stage S2... Regular stage 1 S6... Standby stage 1 S4... Judgment stage 1 S5... Judgment stage 2 S6... Regular stage 2 S7... Standby stage 2 FIG. 7 is a diagram showing input conditions based on combinations of five types of signals.

In the figure, 1'' indicates the presence of the corresponding signal, O'' indicates the absence of the corresponding signal, and for the X mark, the relationship shown in Figure 5 holds regardless of ``0'' or ``1''. shall be.

Each stage will be explained using FIGS. 4 and 5.

(1) 51 non-selected stage: memory devices fh, 11 and Q: '11' or when not accessed from the mask device - J - that is, each address recorder 24, 24'
This is the stage when there is no Ib No. 18.18' (SEL). This stage exists when the input condition (SEL is 0'') in FIG. 5 is met.

(2152 Regular use stage 1: This is a stage that assumes regular use rights. The input conditions when moving from the S1 stage to this 52 stage are ■■■ in FIG. 5.

In this S2 stage, the flip-flop 15 is set as shown in FIG. 1″ output driver 1
When 0 is in the active state, read data can be output. At the same time, the read data or write data is checked for abnormality, and if there is no abnormality, a response signal is returned to the mask device.

If there is an abnormality, the duplex control unit 11 receives the signal 3 (ERR) and sends a reset signal (SET "0", RES
ET'1°') is output to reset the flip-flop 15 to stop its output, thereby inhibiting the output of the output DRIN (10), and the process moves to determination stage S5.

(3) 53 standby stage 1: This is a stage that does not have regular usage rights. The input conditions when moving from the S1 stage to the S6 stage are shown in FIG.

At this time, in FIG. 6, the flip-flop 15 is on standby (if it is in III, it is reset, so the output of the output driver 10 is prohibited.The storage device (11 or 11') in this S6 stage is On the standby side, at this time, the other dual storage device (1
1' or 11) is located on the S2 regular use stage 1, and its flip-flop 15 is set on the regular use side. On the standby side, signal 20 or 21 in Figure 6
By monitoring '(, (?A''), the state of the flip-flop 15 on the regular side can be known. In other words, the flip-flop 15 is set and its output signal 19 (RUN) is 1'' That is, when the signal 18 (SEL) becomes aal", the output of the NAND gate 17 is aO"
The output of NAND gate 17 is NAND gate 1.
7' and the signal on the line 26 is "0", and this is negated by the inverting circuits 22 and 22', and the signal 21.21'(,<CZ) is '1'. However, when the flip-flop 15 is reset, the signal 19 (
RUN) is 0'', and the output of NAND gate 17 is '
1". Therefore, the signal on line 26 is also 1"9, and the negative signals 21 and 21' (ACK) of this signal '1' are
becomes O". In other words, the signal 21.21'(
The fact that A(J) has become O'' indicates that the 7 lip-flop 15 on the regular side has been reset, and it can be seen that an error has been detected on the regular side.

Therefore, the redundancy control section on the standby side sends a set signal (SET&1).
", RESET"0") is output to set the flip-flop 15, and the process moves to the S6 regular stage 2.

(4154 Judgment Stage 1 This is the stage to which storage devices that satisfy the input condition (2) in FIG. 5 when the system starts up transitions.) In FIG. The setting switches 20 and 20' are set exclusively for the storage devices 11 and 11'.If short circuit is set to 0 and open is set to 11, then In FIG. 6, the duplication control device 14 receives 1" as the MST number, and the same <14' receives 0".
In the figure, the first device starts from the master device after system startup.
When the second access is made, the input condition (2) in FIG. 5 is satisfied in the storage device 11, and the storage device 11 moves to the S2 regular stage 1, and the storage device 11' moves to the main stage regardless of the presence or absence of the storage device 11. In this stage, signal 21' (AC
By checking the presence or absence of the storage device 1
The 21 conversion control device 14' of 1' determines the presence or absence of the storage device 11. When the storage device 11 is connected, the 7 lip flop 15 of the storage device 11 is set, the signal 21' (ACK color code signal becomes valid, and the duplication control section 14 of the storage device 11' is activated.
' moves to S6 standby stage 1 and becomes the standby side. If the storage device 11 is not present, the signal 21' (ACK signal) is invalid ('0'), so the duplication control unit 14' of the storage device 11' sets No. 18 (SET '1',
RESET “0”), and its flip-flop 1
5' to 7, transition to S2 regular use stage 1, and become the regular use side.

(5) 55 judgment stage 2: This is a stage to which the system transitions when an abnormality is detected on the regular use side. The presence or absence of the signal 21 (ACK) in FIG. 6 is checked.

After waiting for the reply of signal 21 (ACK) from the standby side, if there is signal 21 (ACK), the storage device on the standby side sets its flip-frog 15 or 15' and returns to S6 regular stage 2. It was determined that the transition had been made to S7.
Move to standby stage 2.

(6156 Regular stage 2: Same as S2 regular stage 1, but this stage does not check for data abnormalities.

(7) S7 standby stage 2: Same as S6 standby stage 1, but in this stage, signal 21 in FIG.
, 21' (ACz) is not monitored.

As described above, when the access from the mask device is completed and the signals 1a, 18' (SEz,) disappear in all the stages, the control of the duplication control section shifts to the non-selection stage 51.

Next, the operation of the dielectric control in the present invention will be explained using FIG. 6, FIG. 4, and FIG. 5. In the following explanation, input conditions ■ to ■ are shown in FIG.
Please refer to Figure 4 for the stages.

When the system is started up, both the storage devices 11 and 11' are in the 51 non-selection stage, and the flip-flops 15 and 15' shown in FIG. 6 are both reset. If the initial setting switch 20 is turned off (Atsr "1") and 20' is turned on (MST "0"), when the first access is received from the master device, the input condition (■) is met in the storage device 11. Established, transition from S1 non-selection stage to S2 regular stage, flip-flop 1
5 is set, the storage device 11 becomes a regular-use device, the input condition (2) is satisfied in the storage device 11', and the process shifts from S1 non-selection stage to 84 judgment stage 1 to S3 Machatsuki stage, and becomes the standby side. From then on, every time there is an access, the input condition (■) is satisfied in the storage device 11 on the regular side, and the transition is made to the S1 non-selection stage - 52 regular stage 1, and the storage device 11 on the standby side
′, the input condition ■ is satisfied, and the S1 non-selection stage-56
They move to the waiting stage 1 and continue to maintain the regular/standby relationship.

Next, when an abnormality is detected in the input/output data for the storage device 11 in the regular storage device 11, an error detection signal 6 (ERR) in the sixth prisoner is output, and the duplication control unit 14 of the storage device 11 is activated. , in the S2 regular stage 1, and based on the result p7 lip-flop 15
is reset, and the process moves to 55 judgment stage 2. When the flip-flop 15 of the storage device 11 is reset, the signal 2V (ACK) is generated in the storage device 11' on the standby side.
disappears. The duplication control unit 14' of the storage device 11' is located in the S6 root stage 1, and its signal 21' (ACz
) Detects the disappearance of Ruto, own flip 70 knob 1
5' and moves to S6 regular use stage 2, which becomes the regular use side. By setting the flip-flop 15' of the storage device 11' which has been on the standby side until now, fg number 21 (ACK) of the storage device 11 which has been on the regular side becomes valid. Since the 21 conversion control unit 14 of the storage device 11 is at the 55 judgment stage, it judges this and moves to the S7 Machitsuki stage 2, becoming the standby side.

From then on, for each access, the input condition (■) is satisfied in the storage device 11 and the process moves to the S1 non-selection stage - 56 root stage 1, and the input condition (2) is satisfied in the storage device 11', and the process moves from the S1 non-selection stage to S2. Transition to regular use stage 1. That is, switching between regular use and standby is performed.

According to the present invention, either one of the storage devices 11 or 11' shown in No. 61.1, that is, one set of storage devices can be mounted and used. At this time, the initial setting switches 20 and 20' are only used to set the priority order for acquiring regular users, so when only one set is used, the initial setting switches 20 and 20' can be set to either on or off. No problem. If set to off ('1'), the sequence goes from 51 non-selection stage S1 to S2 regular stage 1 as described above, and if set to on ('0'), the order goes from S1 non-selected stage to 54 judgment stage 1 → S2 regular stage 52 in order of 1
You can move to regular use stage 1 and acquire regular use rights. Also,
When the storage device according to the present invention is used in a twenty-one configuration, it is sufficient to simply install two sets of storage devices with the same configuration in the same address space.

The duplication control section 14, 14' shown in FIG.
It can be configured as shown in the figure.

In Figure 6, 1.14 is the dual system Thi part 14 in Figure 6.
15 corresponds to the 7 rig 70 tube 15.15' in Figure @6. In the figure, 2
5 is the decision code that programs the state transitions in Figure 4.
Read-only memory (ROM) including tables, etc.
26 is a register, 27 is a stage address ROM
25 and υ are output lines, and 29 is an output line from the ROM 25 of a signal instructing the setting and resetting of the flip-flop 15.

The stage address carried by the output line 27 is transmitted to each stage 51 to S of the duplication control section 14.14' described above.
This is numerical data indicating 7, and in this case, it is represented by numerical information from 1 to 7. This numerical information (stage address) is once latched in the register 26, read out to the line 28 according to the clock CLK, and input into the ROM 25.

ROM25 stores signals (ERR, ACK, RUN, SE
L, MST) input conditions (■ to ■ in Figure 4) and line 2
Enter the stage address information entered from 8, and -
Using these as addresses, the data obtained by indexing the decision table contained in the R0M 25 is output to the set and ring signal output lines 29 and the stage address output line 27 that specifies a new stage. The stage address is
As long as there is no change in the input conditions of the signals (ERR, ACK, RUN, SEL, MST), the clock CLK is circulated between the ROM 25 and the register 26.

According to the present invention, the duplication control section 14, 14' can be realized with a very simple configuration consisting only of a ROM 25 containing a decision table in which state transitions are programmed and a register 26, as shown in FIG.

〔Effect of the invention〕

According to the present invention, when one of the duplexed storage devices is operated as the regular side and the other as the standby side, when an abnormality is detected on the regular side, the system is not disconnected from the system that is in danger of being frequently used, but is simply used. Since the configuration is configured to perform only regular/standby switching, in which the side is switched to the standby side and the standby side is switched to the regular use side, the storage device that was previously switched from the regular use side to the standby side is now switched from the standby side to the regular use side. There is an abnormality in the regular storage device! [This has the effect of being able to be started up immediately as a regular user. In other words, according to the present invention, even if an abnormality occurs in both duplex storage devices, unless the abnormality occurs at the same address, the normal storage device can always be switched to regular use and normal operation can be continued. can. Generally, the probability that two storage devices at the same address will both become abnormal is very small, so the present invention has a great effect on improving the reliability of the operation of the storage devices.

In addition, there is no common part for duplex control, and therefore a duplex configuration can be easily achieved by simply mounting two sets of storage devices in the same address space.

Redundant control number 12, which is to be transferred between storage devices, uses one signal line in time division, so multiple devices can use it in common, which has the effect of minimizing signal line distortion. be.

The state transition of the redundant control unit, which forms the basis of the present invention, is based on the R
It can be easily configured with a small number of parts such as OM and registers, and low cost and high reliability can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a connection diagram of a duplex control power type of a storage device provided with a common duplication control unit according to the prior art, and Fig. 2 is a connection diagram of a duplex control system of a storage device provided with individual duplication control units according to the prior art. , FIG. 3 is a diagram showing the connection configuration of an embodiment of the present invention, FIG. 4 is a state transition diagram of the stages of the duplexing control section according to the present invention, and FIG. 5 is a diagram showing the state transition of the stages of the duplexing control section according to the present invention FIG. 6 is a diagram showing combinations of input conditions, and FIG. 6 is a diagram showing an example of the configuration of a duplication control section in the present invention. 1.1'...Storage unit, 2,2'...Error detection circuit, 6,6'...Error detection signal, 4.4'...Address input, 5,5'...Writing Data, 6,6'...
- Read data, 7, 7'... Duplex control gate signal, 9... System bus, 10.10'... Gate, 11.11'... Storage device, 14.14'... Duplex control section, 15.15'...Flip 70 knob, 1
6゜16'...AND gate, 17.17'...NAND gate, 18' 18γ device select signal (SEL), 19.19
'...Output enable signal (RUN), 20.20'
... Initial setting switch, 21.21'... Duplex control signal (ACK), 22゜22'... Inverting circuit,
26...One signal line, 24.24'...Address decoding section, 25...Read-only memory (R
OM), 26...Register, 27...Stage address output line, 28...Stage address transfer line,
29...Set/reset signal output line, CLK...
clock. % Applicant Fuji Electric Seizo Co., Ltd. (1 other person) Representative Patent Attorney Gobe Tamamushi (3 others) Figure 4Figure 6

Claims (1)

[Claims] It is equipped with two storage devices each having a duplication control section, and one signal line that connects the duplication control sections to each other,
One of the above storage devices is operated as the regular side and the other as the standby side, and when an error is detected in the regular side storage device, the regular side is switched to the standby side storage device, and the standby side is connected to the regular side through the above single signal line. 1. A storage device duplication control method characterized by detecting disappearance of a duplication control signal (ACK) received from a storage device, switching to a regularly used storage device, and continuing a duplication configuration.