JPS6468853A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS6468853A
JPS6468853A JP22702087A JP22702087A JPS6468853A JP S6468853 A JPS6468853 A JP S6468853A JP 22702087 A JP22702087 A JP 22702087A JP 22702087 A JP22702087 A JP 22702087A JP S6468853 A JPS6468853 A JP S6468853A
Authority
JP
Japan
Prior art keywords
read data
stage
holding means
interleave
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22702087A
Other languages
Japanese (ja)
Inventor
Tadashi Kaneko
Kiyoshi Sudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22702087A priority Critical patent/JPS6468853A/en
Publication of JPS6468853A publication Critical patent/JPS6468853A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To shorten the queuing time of a CPU, by checking the start of write at every stage of interleave and starting the read data transfer report to the CPU and a read data holding means after confirming that the stage is idle. CONSTITUTION:An interleave control part 11 is provided with a read data holding means 13 where read data from memory banks 1-4 is held and a control means 12, and this control means checks the start of write it every stage of interleave and starts the read data transfer report to CPUs 5-8 and a read data holding means 13 after confirming that the stage is idle. Thus, when overlapping between transfer of read data and that of write data is forecasted, read data is held in the read data holding means 13 and its transfer can be delayed with one stage as the unit, and the queuing time of CPUs 5-8 is shortened as much as possible.
JP22702087A 1987-09-10 1987-09-10 Memory control system Pending JPS6468853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22702087A JPS6468853A (en) 1987-09-10 1987-09-10 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22702087A JPS6468853A (en) 1987-09-10 1987-09-10 Memory control system

Publications (1)

Publication Number Publication Date
JPS6468853A true JPS6468853A (en) 1989-03-14

Family

ID=16854254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22702087A Pending JPS6468853A (en) 1987-09-10 1987-09-10 Memory control system

Country Status (1)

Country Link
JP (1) JPS6468853A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7325184B2 (en) 1997-06-30 2008-01-29 Matsushita Electric Industrial Co., Ltd. Communications digital signal processor and digital signal processing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7325184B2 (en) 1997-06-30 2008-01-29 Matsushita Electric Industrial Co., Ltd. Communications digital signal processor and digital signal processing method

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