JPS6428753A - Busy managing system for storage device - Google Patents

Abstract

PURPOSE:To reduce the increase of a cycle time due to the waiting for the transfer of writing data by executing a busy management by dividing a next cycle to a writing cycle and a cycle except the writing. CONSTITUTION:In a next reading cycle succeeding to a preceding writing cycle or a reading cycle, a cycle activating EX signal is generated from a memory activating control circuit 1 and the reading cycle is activated by resetting a NFTBSY signal delayed in the resetting time of a second busy register 5 reset by the completion of an ordinary cycle time. In this case, the next operation of a memory is started at the interval of the prescribed off time of the memory. In the succeeding writing cycle to the preceding writing cycle or the reading cycle, when the NSTBSY signal of a first busy register 4 faster by a prescribed time in the resetting time is reset, the EX signal is generated from the circuit 1 and the writing cycle is activated. Accordingly, the increase of the cycle due to the waiting for the transfer of the writing data can be reduced.