JPH0236442A - メモリ管理方法 - Google Patents
メモリ管理方法Info
- Publication number
- JPH0236442A JPH0236442A JP18636088A JP18636088A JPH0236442A JP H0236442 A JPH0236442 A JP H0236442A JP 18636088 A JP18636088 A JP 18636088A JP 18636088 A JP18636088 A JP 18636088A JP H0236442 A JPH0236442 A JP H0236442A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- microprocessor
- data
- interruption
- interrupt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 10
- 238000007726 management method Methods 0.000 claims description 47
- 238000010586 diagram Methods 0.000 description 6
- 210000001217 buttock Anatomy 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18636088A JPH0236442A (ja) | 1988-07-26 | 1988-07-26 | メモリ管理方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18636088A JPH0236442A (ja) | 1988-07-26 | 1988-07-26 | メモリ管理方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0236442A true JPH0236442A (ja) | 1990-02-06 |
| JPH0542019B2 JPH0542019B2 (enExample) | 1993-06-25 |
Family
ID=16187010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18636088A Granted JPH0236442A (ja) | 1988-07-26 | 1988-07-26 | メモリ管理方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0236442A (enExample) |
-
1988
- 1988-07-26 JP JP18636088A patent/JPH0236442A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0542019B2 (enExample) | 1993-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5163146A (en) | System responsive to interrupt levels for changing and restoring clock speed by changing and restoring a register value | |
| JPH0236442A (ja) | メモリ管理方法 | |
| JPH0330175B2 (enExample) | ||
| JPS63318651A (ja) | メモリ管理回路 | |
| JPS603049A (ja) | バスインタ−フエ−ス装置 | |
| JPS62168497A (ja) | 交換処理プログラムにおけるデ−タベ−ス処理方式 | |
| JP3019323B2 (ja) | イメージメモリのダイレクトアクセス方法 | |
| JP3209521B2 (ja) | メモリアクセス制御方法及び計算機システム | |
| JP3037242B2 (ja) | パイプライン処理回路 | |
| JP2594611B2 (ja) | Dma転送制御装置 | |
| JPH0447350A (ja) | 主記憶読み出し応答制御方式 | |
| JP2785855B2 (ja) | 情報処理装置 | |
| JPH086905A (ja) | マルチポートramのアクセス調停回路 | |
| JPH0546547A (ja) | データ処理装置 | |
| JPS63155254A (ja) | 情報処理装置 | |
| JPS60243763A (ja) | デユアルポ−トメモリ制御回路 | |
| JPS5922152A (ja) | 共有メモリのアクセス制御方法 | |
| JPS58129525A (ja) | デ−タ処理システムのデ−タ入出力制御方法 | |
| JPS5942331B2 (ja) | プロセツサソウチノセイギヨホウシキ | |
| JPH0258648B2 (enExample) | ||
| JPH03226850A (ja) | 外部補助記憶制御装置 | |
| JPH02307123A (ja) | 計算機 | |
| JPS63155346A (ja) | Ramチエツク方式 | |
| JPH0457145A (ja) | マルチプロセッサシステム | |
| JPS592297A (ja) | 共有メモリのプロテクシヨン方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |