JPH0236442A - Method for controlling memory - Google Patents

Abstract

PURPOSE:To attain a data processing at high speed without using an expensive memory control element by controlling a data memory through the use of interruption provided in standard in a micro processor. CONSTITUTION:When the micro processor 1 accesses a final address in a control unit which is previously decided for the memory 3, an interruption type memory control circuit 2 normally accesses the memory 3 and simultaneously generates the interruption 14 to the micro processor 1. The micro processor 1 recognizes interruption in an instruction which executes access, detects the termination in the control unit, prepares a new control unit, decides the content of the instruction by a flag which the interruption type memory control circuit 2 has, executes the processing corresponding to the content and continues the data processing again. Thus, interruption can be generated inexpensively compared to a case when a private memory control element is used, and the high speed processing can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a memory management method when data processing is performed using a microprocessor.

[Summary of the invention]

The present invention utilizes a microprocessor that processes data and stores the processed data in memory, in order to manage data memory at high speed.
The data memory is divided into fixed management units, and when the microprocessor writes or reads data to or from the data memory, an interrupt-type memory management circuit monitors the address of the microprocessor and It detects the final address of the management unit, prohibits future data memory write operations, and issues an interrupt to the microprocessor. When the microprocessor receives this interrupt and detects that the management unit has ended, the microprocessor determines whether the instruction that received the interrupt was a write or read, and how many times it has accessed from the final address. Determined by the flag held in the circuit,
For one access, a new management unit is prepared and data processing continues; for multiple accesses, a new management unit is prepared and the previous management unit is used for the new management unit. If you read this, this λ
Data is read from the new management unit for the number of times that have passed, and in the case of writing, write protection is canceled and data is written to the new management unit for the number of times that have passed and the process continues.

[Prior art 1] Conventionally, memory management has been performed by software to determine the management unit, or by a dedicated memory management element or a memory management element built into a microprocessor, or by address conversion in the microprocessor. It was being done.

[Problems to be Solved by the Invention] The problem with conventional methods is that in methods that use a dedicated memory management element, the purpose of using a microprocessor as a high-performance computer is that it does not provide the necessary functions as a computer. Because everything is included, it is extremely expensive for applications that only want to manage data. Furthermore, although the method of managing data memory using software is inexpensive, the data processing speed is slow.

[Means for Solving the Problems 1] In order to solve the conventional problems, the present invention does not use expensive memory management elements and is equipped with a microprocessor as standard so that data processing can be performed at high speed. The configuration uses interrupts to manage data memory.

[Operation] When the microprocessor writes or reads from memory, the memory management circuit monitors the address, and when the final address of the management unit is detected, the memory management circuit generates an interrupt to the microprocessor. . The microprocessor that received the interrupt detects the end of the management unit, prepares a new management unit, determines the content of the instruction that received the interrupt based on the flag held by the memory management circuit, and executes the content. Performs processing according to the data and continues data processing.

E example] Hereinafter, one embodiment of the present invention will be described based on the drawings.

The present invention will be explained in detail using FIG.

When the microprocessor l accesses the memory 3, the address bus 11, the bus control signal 13, and the data bus 12 operate when reading, and the interrupt type memory management circuit 2 recognizes this and performs a predetermined memory 3 If it is not the final address of the management unit, the interrupt type memory management circuit 2 sends the chip select 17 to the memory 3.
, a signal is generated to read 15 or write 16, and normal access is performed. Microprocessor 1 is memory 3
When the last address of the management unit is accessed, the interrupt type memory management circuit 2 generates an interrupt 14 to the microprocessor 1 at the same time as the normal access to the memo 'J3. Microprocessor 1 is
An interrupt is recognized during the instruction performing the access, the end of the management unit is detected, a new management unit is prepared, and the read/write distinction flag and access count distinction flag of the interrupt type memory management circuit 2 are used to After determining the contents of the instruction and performing processing according to the contents, data processing is continued again.

Next, an embodiment of the present invention will be specifically described based on FIGS. 2 and 3. Figure 2 shows the overall block diagram, and Figure 3 shows the overall block diagram.
The figure is a circuit diagram showing the interrupt type memory management circuit 2 in detail.

In this embodiment, the microprocessor 1 has a data bus 1
2 is 16 bits wide, data memory 3 is accessed in units of 1 word (16 bits), and instructions for accessing data memory 3 are 1 word access performed in one access, or 1 word access performed in 2 accesses. A case will be described in which 2-word access is performed and 2 kilobytes are used as the memory management unit.

When the microprocessor 1 writes to or reads from the data memory 3, the bus control signal 13 and address bus 11 of the microprocessor 1 are input to the address decoder 4, and the address decoder 4 outputs the data memory withdrawal signal ( RAMSELECT) 23 generates 0 interrupt type memory management circuit 2, select signal 23
and receives the bus control signal 13 of the microprocessor 1.
is part of. Bus read/write control signal (R/W
)18 as well as a memory control signal C517. RD15WR16 are supplied from the memory R/W control block 2D in FIG. At the same time, the interrupt type memory management circuit 2 determines whether or not the access is to the final address of the memory management unit.
The address bus 11 is controlled by the NAND gate 2A shown in the figure.
The determination is made based on whether the lower address lines of A1 to AIO are all 1. If the address is the final address, 0 is latched in F/F 2 B at the start of the bus cycle, and the
The output of F is an interrupt (INT
)14. At the same time, the F/F 2C holds information as to whether the access by the microprocessor 1 is for reading or writing. At the end of the bus cycle, F/F2E
becomes 0, the memory control signal (WR) 1B is disabled, and the data memory 3 is disabled until the interrupt clear signal (INTCLR) 20 is given from the microprocessor l.
Any operation that rewrites the is prohibited. F/Fs 2F and 2G are given an interrupt clear signal (INTCLR) 20 in advance, and both are held at 1. When the access to the final address ends with one word, F/F 2 F
0 is held in F/F2G, 1 is held in F/F2G, and when the last address is accessed with two words from the last address, 0 is held in F/F2F and 0 is held in F/F2G. be done. When the microprocessor 1 receives an interrupt, the output R/W flag 19 of F/F 2 B,
F output flag A24, F/F2G output flag B2
5 is read from the I10 port 5 via the address decoder 4 by the status read signal (INPORTSEL) 21, and the contents of the instruction cycle in which the interrupt has been accepted are determined. If the contents of F/F2B, 2F, and 2G are 101, it indicates that the reading process ended at the last address of the memory management unit, a new management unit for reading is prepared, and an interrupt clear signal (INTCL
R) Issue 20 and continue data processing again. F/F
If the contents of 2B, 2F, and 2G are 100, this indicates that one word has been read beyond the final address of the memory management unit during the reading process, a new management unit is prepared for reading, and an interrupt clear signal ( INTCLR) 20 is issued, the first word of the new management unit is read into the internal register of the microprocessor 1 that has been set in advance for reading, and data processing is resumed. In the case of 001, the process indicated by lot is processed as a write, and in the case of 000, the process indicated by 001 is processed as a write.

In this embodiment, the case where the data bus width is 16 bits has been explained as an example, but it can be realized with almost the same circuit in the case of other microprocessors, and the F/F2F, This can be easily realized by increasing the number of F/F2Gs.

[Effects of the Invention] As stated above, the present invention can configure data memory management using a very small number of parts, so it can be created at a lower cost than when using a dedicated memory management element, and software can be created without using the present invention. When memory management is performed using , an instruction to compare memory addresses is entered for each data item in order to determine the boundaries of management units, which makes it very slow6.
By using the present invention, there is no comparison instruction, and high-speed processing can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an outline of the present invention. FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram showing an embodiment of the present invention.・Microprocessor ・Interrupt type memory management circuit ・Data memory ・Address decoder ・I10 boats and above Applicant Seiko Electronics Co., Ltd. Representative Patent attorney Takayuki Hayashi Child 1 Figure Buttocks 20

Claims (1)

[Claims] In a method for managing memory by dividing data memory into fixed units, when a microprocessor writes or reads data to or from the memory, the address of the microprocessor is monitored, and the memory is divided into fixed units. detecting the final address and generating an interrupt to the microprocessor, and at the same time prohibiting writing to the memory after accessing the final address;
By holding a flag that distinguishes whether the access to the final address is a read or a write, and by holding a flag that indicates how many times the instruction that generated the interrupt has accessed from the final address, the memory for data can be A memory management method for managing.