JPH0234465B2 - - Google Patents

Info

Publication number
JPH0234465B2
JPH0234465B2 JP57068412A JP6841282A JPH0234465B2 JP H0234465 B2 JPH0234465 B2 JP H0234465B2 JP 57068412 A JP57068412 A JP 57068412A JP 6841282 A JP6841282 A JP 6841282A JP H0234465 B2 JPH0234465 B2 JP H0234465B2
Authority
JP
Japan
Prior art keywords
semiconductor
substrate
electrode
functional element
acoustic wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57068412A
Other languages
English (en)
Other versions
JPS58184753A (ja
Inventor
Shoji Takishima
Tomoyuki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP57068412A priority Critical patent/JPS58184753A/ja
Publication of JPS58184753A publication Critical patent/JPS58184753A/ja
Publication of JPH0234465B2 publication Critical patent/JPH0234465B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Description

【発明の詳細な説明】 本発明は、異種機能素子同士が共通支持基板上
に配置された複合半導体装置の製造方法の改良に
間するものである。
各種半導体素子における半導体キヤリアとこれ
とは異なつた他の機能素子例えば弾性表面波素子
における弾性表面波とを結合させることにより、
減衰、増幅等の線型結合あるいはコンボリユーシ
ユン、コリレーシヨン等の非線型結合現象を利用
した表面波増幅器や表面波コンボルバ等の研究、
開発が盛んに行われている。このためには半導体
素子を構成するシリコン、−Ｖ族金属間化合物
等の半導体基板と機能素子を構成するLiNbO3、
LiTaO3等の圧電基板とを一体的に組み合せるこ
とが行われる。第１図はこのようにして得られた
複合半導体装置の従来構造を示すもので、１は支
持基板、２はリード、３は半導体素子、４は弾性
表面波素子、５，６は上記素子３，４表面に各々
設けられた電極、７は電極５，６同士あるいは上
記電極５，６とリード２間を接続するボンデイン
グワイヤで、半導体素子３および弾性表面波素子
４は支持基板１上に配置された構成となつてい
る。
しかしながらこのように異種材料から成る基板
を一体的に組み合せるには問題がある。
例えば上記弾性表面波素子４表面に形成される
電極６は、１〜2μパターン幅ですだれ状に設け
られたトランスジユーサと称される弾性表面波を
発生させるためのものでアルミニウム等で構成さ
れ、一方半導体素子３表面には５〜6μパターン
幅の電極５が形成され、これら両電極５，６間は
上記ボンデイングワイヤ７によつて接続される
が、上記のように微細幅の電極同士でワイヤボン
デイングを良好に行うのは極めて困難である。し
たがつて目的とする特性を得るのが難かしくな
る。
本発明は以上の問題に対処してなされたもの
で、半導体素子とこれとは異なつた他の機能素子
とが該機能素子の両側が半導体素子によつて囲ま
れるように共通の支持基板上に配置され、上記半
導体素子及び機能素子表面に両者間を接続する配
線が形成される複合半導体装置の製造方法であつ
て、 (a) 両端部に半導体素子が形成された半導体基板
を用意する工程と、 (b) 上記半導体基板の両端部を支持基板上に固定
する工程と、 (c) 上記固定された半導体基板の中間部を除去し
て支持基板を部分的に露出せしめる工程と、 (d) その露出した支持基板上に上記他の機能素子
を上記半導体基板と略同一平面と成るように固
定する工程と、 (e) 上記半導体基板と他の機能素子との間の隙間
に絶縁物を埋込む工程と、 (f) 上記他の機能素子上に電極を形成すると共
に、該電極と上記半導体素子とを電気的に接続
する配線を形成する工程と、より成ることを特
徴とする。
以下図面に示す実施例を参照して本発明を説明
すると、第２図は本発明の対象とする複合半導体
装置を示す上面図で第１図と同一部分は同一番号
で示し、弾性表面波素子４はその両側が半導体素
子３によつて囲まれるように共通の支持基板１上
に配置され、上記弾性表面波素子４および半導体
素子３表面には両者間を接続するように配線８が
形成される。また弾性表面波素子４および半導体
素子３間には絶縁物９が介在されて両者は電気的
に分離される。
以上の構造の複合半導体装置は例えば第３図に
示す本発明の一実施例の製造方法によつて得るこ
とができる。以下第３図ａ〜ｆを参照して工程順
に説明する。
工程〔Ａ〕：第３図ａのように、所望の半導体
素子３がその両端部Ａ，Ｂに予め形成された半導
体基板１０を用意する。上記半導体素子３表面に
は既に必要な電極５が形成され、検査が完了して
良品のもののみが用いられる。基板１０の中央部
Ｃには半導体素子が形成されても、されなくとも
よい。
工程〔Ｂ〕：第３図ｂのように、上記基板１０
の両端部Ａ，Ｂの裏面を接着材１１を介して支持
基板１上に固定する。接着材１１および支持基板
１は絶縁性のものでも導電性のものでもよい。
工程〔Ｃ〕：第３図ｃのように、基板１０の中
央部Ｃをダイシング技術により切断して除去する
ことにより隙間１２を形成する。
工程〔Ｄ〕：第３図ｄのように、圧電基板１３
を上記隙間１２から接着材１１を介して支持基板
１上に固定する。この段階では上記基板１３には
未だ電極等が形成されていない。
工程〔Ｅ〕：第３図ｅのように、上記隙間１２
の残りの部分（約50〜60μ幅）に絶縁物９を埋め
込んで、上記圧電基板１３と半導体素子３間を電
気的に絶縁する。
工程〔Ｆ〕：第３図ｆのように、周知の金属薄
膜形成技術およびフオトリソグラフイー技術を利
用して、上記圧電基板１３表面にトランスジユー
サとして働くすだれ状電極６を含む種々の電極を
形成することにより弾性表面波素子４を完成す
る。
これと同時に上記弾性表面波素子４表面上の電
極と前記半導体素子３表面上の電極とを接続する
ための配線８を形成する。以上によつて第２図の
ような構造の複合半導体装置が得られる。
上記製法によれば、支持基板１上に予め半導体
素子３を固定しこの半導体素子３間に設けられた
隙間１２を利用して圧電基板１３を固定した後弾
性表面波素子４を形成するようにしたものである
から、弾性表面波素子（圧電基板）を固定するた
めの位置決めを容易に行うことができる。よつて
上記両素子間を接続するための配線も微細パター
ンで高精度に形成することができる。
以上述べて明らかなように本発明の製造方法に
よれば、機能素子の両側が半導体素子によつて囲
まれるように両素子が共通支持基板上に配置さ
れ、上記半導体素子および機能素子表面に両者間
を接続する配線を形成するように構成された複合
半導体装置を容易に製造することができ、特に機
能素子の位置決めが容易で、しかも上記両素子間
を微細かつ高精度パターンの配線により接続でき
る。よつて目的とする特性を容易に得ることがで
きる。
なお機能素子の一例としては弾性表面波素子を
挙げたが何らこれに限定されるものではない。
【図面の簡単な説明】
第１図および第２図は従来および本発明の対象
とする複合半導体装置を示す斜視図、第３図ａ〜
ｆはいずれも本発明実施例を示す断面図である。 １……支持基板、３……半導体素子、４……弾
性表面波素子（他の機能素子）、５，６……電極、
８……配線、９……絶縁物。

Claims (1)

  1. 【特許請求の範囲】 １ 半導体素子とこれとは異なつた他の機能素子
    とが該機能素子の両側が半導体素子によつて囲ま
    れるように共通の支持基板上に配置され、上記半
    導体素子及び機能素子表面に両者間を接続する配
    線が形成される複合半導体装置の製造方法であつ
    て、 (a) 両端部に半導体素子が形成された半導体基板
    を用意する工程と、 (b) 上記半導体基板の両端部を支持基板上に固定
    する工程と、 (c) 上記固定された半導体基板の中間部を除去し
    て支持基板を部分的に露出せしめる工程と、 (d) その露出した支持基板上に上記他の機能素子
    を上記半導体基板と略同一平面と成るように固
    定する工程と、 (e) 上記半導体基板と他の機能素子との間の隙間
    に絶縁物を埋込む工程と、 (f) 上記他の機能素子上に電極を形成すると共
    に、該電極と上記半導体素子とを電気的に接続
    する配線を形成する工程と、より成ることを特
    徴とする複合半導体装置の製造方法。 ２ 上記他の機能素子が弾性表面波素子であり、
    また上記電極がトランスジユーサとしての電極で
    あることを特徴とする特許請求の範囲第１項記載
    の複合半導体装置の製造方法。
JP57068412A 1982-04-23 1982-04-23 複合半導体装置の製造方法 Granted JPS58184753A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57068412A JPS58184753A (ja) 1982-04-23 1982-04-23 複合半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57068412A JPS58184753A (ja) 1982-04-23 1982-04-23 複合半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS58184753A JPS58184753A (ja) 1983-10-28
JPH0234465B2 true JPH0234465B2 (ja) 1990-08-03

Family

ID=13372929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57068412A Granted JPS58184753A (ja) 1982-04-23 1982-04-23 複合半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS58184753A (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6142943A (ja) * 1984-08-06 1986-03-01 Clarion Co Ltd 複合半導体装置の製造方法
JPH0728003B2 (ja) * 1986-11-10 1995-03-29 松下電器産業株式会社 薄膜ハイブリツドｉｃ

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56115553A (en) * 1980-02-18 1981-09-10 Fujitsu Ltd Method of mounting integrated circuit
JPS5943826A (ja) * 1982-09-04 1984-03-12 Sumitomo Metal Ind Ltd 高靭性電縫鋼管の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56115553A (en) * 1980-02-18 1981-09-10 Fujitsu Ltd Method of mounting integrated circuit
JPS5943826A (ja) * 1982-09-04 1984-03-12 Sumitomo Metal Ind Ltd 高靭性電縫鋼管の製造方法

Also Published As

Publication number Publication date
JPS58184753A (ja) 1983-10-28

Similar Documents

Publication Publication Date Title
JP3610364B2 (ja) 医療画像化のための多重圧電層超音波変換器
US20010011857A1 (en) Surface acoustic wave device and method for fabricating the same
JP3308759B2 (ja) 弾性表面波装置
JP2013501405A (ja) 集積電気接続を備えた超音波イメージング変換器音響スタック
JP5269301B2 (ja) 弾性表面波装置
US4291285A (en) Surface acoustic wave device and method of manufacturing
US4843035A (en) Method for connecting elements of a circuit device
JPS58172008A (ja) 圧電振動子の構造及びその製造方法
JP6590843B2 (ja) 弾性波デバイス
JP2001509901A (ja) 音響プローブの製造方法
JPH0234465B2 (ja)
US4604594A (en) Surface wave filter having photoresist damping material thereon and method for manufacturing the same
JPH05275963A (ja) 弾性表面波フィルタ
JP2021027383A (ja) 弾性波装置
JPS6142943A (ja) 複合半導体装置の製造方法
JPS59119999A (ja) 超音波トランスジユ−サ
JP3206187B2 (ja) チップ型圧電共振子の製造方法
JP2991837B2 (ja) 弾性表面波フィルタ
JPH10215143A (ja) 弾性表面波装置
JPH04367111A (ja) 圧電振動子の製造方法
JPH0241924B2 (ja)
JPS5825254A (ja) 半導体装置およびその製法
JPS605629Y2 (ja) 圧電振動子
JPH0411440Y2 (ja)
JPS6120409A (ja) 表面弾性波素子の製造方法