JPH0232561A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To acquire a high precision MIS capacitor by providing a capacity of a structure which is provided with an electrode through a dielectric layer on an impurity region of a semiconductor substrate, by enclosing the impurity region by the capacity, and by forming a second dielectric layer which is arranged between the electrode and a first dielectric layer only on a field insulating layer. CONSTITUTION:A capacity is provided wherein an electrode 16 is arranged through a first dielectric layer 12 and a second dielectric layer 15 of a silicon nitride film and an ASSG layer on an impurity region 17 of a semiconductor substrate 1 of a semiconductor device. The capacity encloses the impurity region 17, a field insulating film 11 is provided to a surface of the substrate 1, and the first dielectric layer 12 extends onto the insulating film 11 and the impurity region 17. The second dielectric layer 15 is arranged between the electrode 16 and the first dielectric layer 12 only on the insulating film 11, and the first dielectric layer which is provided to the upper section thereof is provided to the impurity region to prevent the capacity from being affected by the second dielectric layer.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device in which a MIS capacitor is provided on a substrate and a method for manufacturing the same, and in particular, a highly accurate MIS capacitor can be obtained even by a reflow process. The present invention relates to a semiconductor device and a method for manufacturing the same.

(Summary of the Invention) The present invention provides a semiconductor device in which a MIS capacitor is provided on a substrate, in which a first dielectric layer is provided over an impurity region formed on the substrate and a field insulating film surrounding the impurity region. A highly accurate MIS capacitor can be obtained by forming a second dielectric layer on the field insulating film and providing a second dielectric layer between the field insulating film and the electrode, and also provide a suitable manufacturing method thereof.

[Conventional technology]

When forming a capacitor in a monolithic IC, an MIS capacitor is often used, which is formed by sandwiching a dielectric material between an emitter diffusion layer of a semiconductor substrate and a metal electrode.

By the way, the above MXS capacitor at -111Q can be used with bipolar transistors, nMO3) transistors, p
MO3) is formed on the same semiconductor substrate together with elements such as transistors. In such devices, as the wiring of devices such as bipolar transistors has become finer and more highly integrated, measures have been taken to prevent the wiring from breaking. This is done by forming a glue flow film such as PSG or As5G on the base of the wiring layer and applying heat treatment to form a taper in the contact portion.

[Problem to be solved by the invention]

By the way, in the case of the above-mentioned process, as shown in FIG. 3a, in the MIS capacitor, an opening 103 is formed on the semiconductor substrate 101, or the flow film 102 is reflowed. At the same time, a taper is formed in the contact portion of an element such as a bipolar transistor. And the third
As shown in the figure, the opening 10 of the reflow film 102
3, a dielectric layer 104 forming a capacitor is formed. Finally, as shown in FIG. 3C, a reflow process using heat treatment is performed again for the purpose of alleviating the step differences in the contact portions of other elements.

After the dielectric layer 104 is formed in this way, if heat treatment is performed again and the flow film 102 near the opening 103 is reflowed again, the dielectric J! Peeling or swelling occurs at the boundary portion 106 with 5104, resulting in deterioration of the accuracy of the capacitance of the MIS capacitor.

Therefore, the present invention was proposed in view of the above-mentioned conventional situation, and an object of the present invention is to provide a semiconductor device that can realize a high-precision MIS capacitor, and further improves the capacitance. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve precision and can be easily combined with manufacturing processes for other elements formed on the same semiconductor substrate.

[Means to solve the problem]

The present invention has been proposed to achieve the above-mentioned object, and provides a semiconductor device having a capacitance structure in which an electrode is provided on an impurity region of a semiconductor substrate via a dielectric layer. A field insulating film surrounding the impurity region and formed on the surface of the semiconductor substrate, a first dielectric layer extending over the field insulating film and the impurity region, and an electrode formed only on the field insulating film. and the first dielectric layer.

Here, examples of materials that can be used for the first dielectric layer include SiN, SiO□, or a combination thereof. Furthermore, for the second dielectric layer, materials such as As5GSPSG, BSG, BPSG, etc. can be used.

Further, the present invention includes a step of forming a field insulating film having a first opening on a semiconductor substrate, a step of forming an impurity region in the first opening of the semiconductor substrate and in a contact electrode formation portion, and a step of forming a first dielectric layer excluding the contact forming portion; and having an opening larger than the first opening in the first opening, and having an opening in the contact electrode forming portion. The method includes the steps of forming a second dielectric layer, heating and fluidizing the second dielectric layer, and forming electrodes on respective openings of the second dielectric layer. It is characterized by:

[Operation] Since the second dielectric layer is formed only on the field insulating film, only the first dielectric layer having an electrode provided thereon is formed on the impurity region of the semiconductor substrate. Therefore, the capacitance is not affected by the second dielectric layer, and the value of the capacitance can be accurately determined from the first dielectric layer sandwiched between the impurity region and the electrode.

Further, in the manufacturing method, a first dielectric layer is formed on a field insulating film having a first opening, and a second dielectric layer having an opening larger than the first opening is formed on the first dielectric layer. Therefore, even if the second dielectric layer is reflowed by heating, the capacitance is almost determined only by the area of the first opening, and there is no influence of the flow of the second dielectric layer.

〔Example〕

Hereinafter, the semiconductor device according to the present invention will be referred to as an MIS capacitor,
Bipolar transistor, pMOS transistor and n
A case in which MO3) transistors are formed on the same semiconductor substrate will be described with reference to the drawings.

A p-type semiconductor substrate 1 on which various elements such as MIS capacitors and bipolar transistors are formed has an n-type buried layer 6 diffused into a part of its surface, and an n-type buried layer 6 on the top thereof.
A type epitaxial layer 7 is deposited and furthermore this n
A p-type element isolation region 8 is formed to separate the −-type epitaxial layer 7 into several island regions.

The portion of the semiconductor substrate 1 where the MIS capacitor 2 is formed is the surface portion of the n-type epitaxial layer 70, and the first opening 9 of the MIS capacitor 2 has an opening width W1.
An impurity region 17 formed by introducing an n0 type impurity into the contact electrode forming portion 10 is provided. Further, an n'' type plug-in region 29 is formed below this impurity region 17 and between it and the n'' type buried layer 6. A field insulating film 11 is formed by selective oxidation in a shape in which the first opening 9 and the contact electrode forming part 10 are opened. Further, a silicon nitride film 1 as a first dielectric layer is formed on the field insulating film 11 and the first opening 9 except for the contact electrode forming part 10.
2 is formed.

On this silicon nitride film 12, a second dielectric layer A3 is formed, in which an opening 13 having an opening width W2 wider than the first opening 9 and an opening 14 for forming a contact electrode are formed.
30 layers 15 are formed with a taper by reflowing the Ag2O layer 15. Further, an A1 wiring 16 is formed on the first opening 9 and the contact electrode forming portion 10.

The reason why the opening 13 with the opening width W2 of the As2O layer 15 formed on the first opening 9 with the opening width W1 is formed wider than the opening width of the first opening 9 is as follows. Pig As
5GJ! This is to prevent the side wall of the opening 13 from covering the first opening 9 when the W15 is reflowed.

By doing so, the capacitance of the MIs capacitor can be maintained with high precision even if the As2O layer 15 is reflowed.

Furthermore, this p-type semiconductor substrate 1 is provided with a bipolar transistor 3, a pMoS transistor 4, and an nMO3) transistor 5.

As shown in FIG. 1, a semiconductor in which a p-type element isolation region is formed to separate an n3-type buried layer N6, an n-type epitaxial layer 7, and this n-type epitaxial layer N7 into several island regions. On the substrate 1 are an emitter region 18, a base region 19 . Collector extraction area 20 and 9 MO3) transistor 4 and nM
O3) Impurity regions forming the source regions 21, 23 and drain regions 22, 2.4 of the transistor 5 are formed. Also, in the lower part of the collector take-out area 20, n
An n-type plug-in region 29 is formed between the °-type buried layer 6 and the n-type plug-in region 29 .

Then, facing the surface of the semiconductor substrate 1, a field insulating film 11 is formed by selective oxidation so as to isolate the bipolar transistor 3, the 9MO3) transistor 4, and the nMO3) transistor 5. Also, 9
MO3) A gate electrode 25.26 is formed between the source region 2123 and drain region 22.24 of the transistor 4 and the nMOS transistor 5 with a gate insulating film 27.28 interposed therebetween.

On the field insulating film 11, an emitter region 1B, a base region 19. Collector region 20, pMOS transistor 4 and nMOS
A silicon nitride film 12 and an As5G layer 15 are laminated with openings formed in the electrode formation portions of the source region 21.23 and drain region 22.24 of the transistor 5. The opening of the As5G layer 15 is tapered by reflow. An electrode 16 made of Al is formed in each opening.

In this way, by reflowing the As5G layer in each electrode forming portion, breakage of the electrodes can be prevented, and a highly reliable device can be formed.

Further, in the above semiconductor device, the field oxide film and the As
The silicon nitride film formed between the 5G layer also functions as a film for preventing field inversion.

Next, regarding the method for manufacturing a semiconductor device according to the present invention,
In particular, an example applied to a MIS capacitor will be described with reference to the drawings.

First, as shown in FIG. 2A, an n° type buried layer 52 is diffused and formed on a part of the surface of a p type semiconductor substrate 51, and then an n- type epitaxial layer 53 is deposited on top of the n° type buried layer 52. Then, p-type element isolation regions 54 are formed so as to separate this epitaxial layer 53 into several island regions.

Then, a field insulating film 59 is formed on the semiconductor substrate 51 using a silicon nitride film.

This field insulating film 59 has a first opening 55 having an opening width WI and a contact electrode forming portion 56 having a predetermined opening width.

Subsequently, the surface of the semiconductor substrate 51 is oxidized to form the first opening 5.
A pad oxide film 60 is formed on the contact electrode forming portion 5 and the contact electrode forming portion 56. Then, an n-type impurity is introduced into the surfaces of the first opening 55 and the contact electrode forming portion 56 to form an n-type impurity region 61. Further, in order to improve the characteristics of this semiconductor device, an n plug-in region 62 is formed under the n-type impurity region 61.

Subsequently, as shown in FIG. 2, pad oxidation It! is formed in the first opening 55. 60, a photoresist 63 is formed over the entire surface and the first opening 55 is removed.
The window is opened using a mask having a wider opening width W. Then, the pad oxide film 60 formed in the first opening 55 is removed by wet etching.

Thereafter, the photoresist 63 is removed, and as shown in FIG. 2C, a silicon nitride film 65 as a first dielectric layer is formed over the entire surface of the semiconductor substrate 51 by CVD under low pressure conditions. Then, an As5G layer 66 as a second dielectric layer is formed thereon by CVD.

Next, in order to form an opening 67 having an opening width W2 larger than the opening width W1 of the first opening 55 in the As5Gtii 66, a photoresist is applied over the entire surface for 6 days as shown in FIG. The mask is the same as that used in the process of forming and removing the pad oxide film 60, and has an opening width W of the first opening and a larger opening width W above the first opening. A window is opened in the photoresist 68 using a photoresist, and an opening 67 having an opening width W2 is formed in the As5G166 by wet etching.

Subsequently, as shown in FIG. 2e, a photoresist 69 is formed over the entire surface, a window is opened in the photoresist 69 at a location corresponding to the contact electrode formation portion 56, and the photoresist 69 is used as a mask. As5GN66,
The silicon nitride film 65 and the bad oxide film 60 are etched away by RIE to form an opening 70.

Then, as shown in FIG.
．． After forming a taper in 70 and subsequently applying aluminum wiring over the entire surface, patterning is performed to form electrode 71.

By manufacturing a semiconductor device as described above, the selective oxidation process and the flow process can be performed in common with the manufacturing process of other elements formed on the same semiconductor substrate. A semiconductor device in which a transistor, a pMOS transistor, an nMOS transistor, etc. are formed simultaneously can be easily manufactured.

In addition, since wet etching is used to remove the padded oxide film and the Ag2O layer to form the first opening, it may damage the surface of the first opening, etc. It is possible to form a capacitor with high breakdown voltage and high accuracy without any problems.

Furthermore, since the mask used to remove the band oxide film and the mask used to form the first opening in the Ag2O layer can be used in common, the process can be simplified and costs can be reduced.

Note that the method for manufacturing a semiconductor device according to the present invention may be modified without departing from the gist of the present invention.

〔Effect of the invention〕

As is clear from the above description, in the semiconductor device of the present invention, since the second dielectric layer is formed only on the field insulating film, no electrode is provided on the impurity region of the semiconductor substrate. Only the first dielectric layer is formed. Therefore, the capacitance is not affected by the second dielectric layer, and the value of the capacitance can be accurately determined from the first dielectric layer sandwiched between the impurity jI region and the electrode.

Further, in the manufacturing method, a first dielectric layer is formed on a field insulating film having a first opening, and a second dielectric layer having an opening larger than the first opening is formed on the first dielectric layer. Therefore, even if the second dielectric layer is reflowed by heating, the capacitance is almost determined only by the area of the first opening, and there is no influence from the flow of the second dielectric layer. A precision M■S capacitor can be realized.

The selective oxidation process and flow process performed to form this MIS capacitor can be performed in common with the manufacturing process of other elements formed on the same substrate, so MIS
A semiconductor device that combines an S capacitor with a bipolar transistor, a 9MO3) transistor, an nMOS transistor, etc. can be easily manufactured.

[Brief explanation of the drawing]

The first is a schematic cross-sectional view showing an example of a semiconductor device to which the present invention is applied. FIGS. 2a to 2f are schematic sectional views sequentially showing a method for manufacturing a semiconductor device according to the present invention. FIGS. 3A to 3C are schematic cross-sectional views showing an example of a conventional method for manufacturing a semiconductor device. 67.70...opening

Claims (2)

[Claims] (1) In a semiconductor device having a capacitor having a structure in which an electrode is provided on an impurity region of a semiconductor substrate via a dielectric layer, the capacitance is a field insulating film surrounding the impurity region and formed on the surface of the semiconductor substrate. a first dielectric layer extending over the field insulating film and the impurity region; and a second dielectric layer extending only over the field insulating film and between the electrode and the first dielectric layer. 1. A semiconductor device comprising a dielectric layer. (2) a step of forming a field insulating film having a first opening on the semiconductor substrate; a step of forming an impurity region in the first opening of the semiconductor substrate and in a contact electrode formation portion; and forming the contact. forming a first dielectric layer excluding the first dielectric layer; and a second dielectric layer having an opening larger than the first opening in the first opening and having an opening in the contact electrode forming part. a step of forming a dielectric layer; a step of heating and fluidizing the second dielectric layer; and a step of forming electrodes on respective openings of the second dielectric layer. Production method.