JP3048796B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit capable of reflowing a contact hole at a lower temperature than before.

[0002]

2. Description of the Related Art In recent semiconductor integrated circuits, a flattening technique for making a step on a surface gentle is indispensable in order to increase the density of electrode wiring. The most typical flattening technique is a flow of an interlayer insulating film, and a boron phosphorus silicate glass (BPSG) film is often used. According to this technique, the BPSG film is heated and softened to absorb the step of the base and to make the shape of the contact hole gentle.

FIGS. 6 and 7 show a contact hole reflow step of a conventional semiconductor integrated circuit in the order of steps. First, as shown in FIG. 6 (A), a MOSFET comprising, for example, a gate electrode (2) and source / drain regions (3) is formed on the surface of a semiconductor substrate (1), and a gate is formed as shown in FIG. 6 (B). A BPSG film (6) covering the surface of the electrode (2), the gate oxide film (4) and the LOCOS oxide film (5) is formed, and a heat treatment at about 900 ° C. is performed as shown in FIG. The surface of the BPSG film (6) is made smooth by flowing it, and as shown in FIG. 7A, a contact hole (7) penetrating the BPSG film (6) and the gate oxide film (4) is formed by photoetching. The BPSG film (6) is formed, and is again subjected to a heat treatment at about 900 ° C. as shown in FIG.
The shape of the contact hole (7) is made gentle. Then, the source material is deposited by aluminum material deposition and photo etching.
This is for forming a drain electrode (8) (for example, Japanese Patent Application Laid-Open No. 02-135733).

[0004]

However, the conventional process involves 9 steps in the flow and reflow steps of the BPSG film (6).
Since the high-temperature heat treatment at about 00 ° C. is performed twice, there is a disadvantage that the diffusion region formed previously is re-diffused and the element characteristics vary.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has been made by performing a reflow process of a BPSG film by depositing a silicon nitride film instead of a simple heat treatment. Another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit, which can omit one high-temperature heat treatment. It is another object of the present invention to provide a method of manufacturing a semiconductor device in which a manufacturing process is simplified by sharing formation of a silicon nitride film with formation of a dielectric thin film of a capacitor.

[0006]

According to the present invention, even if the flow step of the BPSG film (6) is the same as the conventional one, the reflow step after the formation of the contact hole (7) can be performed at a lower temperature than the conventional one, so that the heat treatment is reduced accordingly. Can be.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. 1 and 2 are cross-sectional views illustrating a method for manufacturing a semiconductor integrated circuit according to the present invention. As an example, a portion where a MOSFET element is formed on a substrate will be described. Referring to FIG. 1A, an MO is formed on a semiconductor substrate (1).
An SFET device is formed. First, a silicon nitride film is deposited on the surface of the semiconductor substrate (1) to form an oxidation-resistant mask, and the surface of the substrate (1) is selectively oxidized to obtain a LOCO.
An S oxide film (5) is formed. After the oxide film on the surface of the substrate (1) is once removed, gate oxidation is performed to form a clean gate oxide film (4) on the surface, and a polysilicon material is deposited thereon. After the polysilicon material is subjected to phosphating to impart conductivity, the polysilicon material is photo-etched to form a gate electrode (2). still,
(9) is an electrode wiring made of a polysilicon material formed on the LOCOS oxide film (5). Thereafter, a resist mask is formed on the surface of the substrate, and P-type or N-type source / drain regions (3) are formed by ion-implanting impurities.

Referring to FIG. 1B, a BPSG film (6) having a thickness of 0.4 to 0.6 .mu.m is deposited on the entire surface by normal pressure CVD. At this stage, the shape of the surface of the BPSG film (6) has a large step due to the step of the base. Referring to FIG. 1C, a BPSG film (6) is flowed by subjecting the entire substrate (1) to a heat treatment at about 900 ° C. for several tens of minutes. By the flow process, the shape of the surface of the BPSG film (6) becomes smooth, and fine processing can be performed by forming contact holes.

Referring to FIG. 2A, a contact hole (7) penetrating through a BPSG film (6) and a gate oxide film (4) is formed by photoetching. The contact hole (7) is formed by forming the shape of the vertical wall into a vertical wall by anisotropic etching, or forming the lower half of the film thickness into a vertical wall by anisotropic etching and the upper half into a tapered shape by isotropic etching. It may be a combination.

[0010] With reference to FIG. 2 (B), the silicon nitride film 400~600Å the entire surface by LP C VD method (10)
Is deposited. By the heat treatment at 700 to 800 ° C. for several minutes, the BPSG film (6) is reflowed, and the shape of the contact hole (7) becomes gentle. Usually BPS
The reflow temperature of the G film (6) is around 900 ° C. Therefore, it is considered that the heat treatment given by the deposition process of the silicon nitride film (10) hardly changes the shape of the BPSG film (6). However, the BPSG film (6) and the silicon nitride film (10) have significantly different coefficients of thermal expansion, and this difference probably causes the silicon nitride film (10) to push the BPSG film (6) as shown in FIG. The force in the direction of the arrow (11) is applied, and the BPSG film (6) is excessively reflowed by a synergistic action with the contraction force of the BPSG film (6) which is the force in the same direction.
It is thought to be.

Referring to FIG. 2C, after removing the silicon nitride film (10), an electrode material such as aluminum or aluminum silicon is sputter-deposited on the entire surface.
This is photoetched to form an electrode wiring (8). According to the above manufacturing method of the present invention, BPSG
Since the reflow process of the film (6) is performed simultaneously with the deposition process of the silicon nitride film (10), heat treatment can be performed at a low temperature. Therefore, re-diffusion of the diffusion region of an already formed element can be suppressed, and variations in element characteristics such as MOSFET elements can be reduced.

The shape change of the BPSG film (6) due to the deposition of the silicon nitride film (10) depends to some extent on the volume of the BPSG film (6). FIG. 3 is a cross-sectional view showing a difference in shape change depending on the volume of the BPSG film (6). FIG.
3A shows the state before the silicon nitride film 6 is deposited, FIG. 3B shows the state after the deposition, and FIG. 3C shows the state after the silicon nitride film 6 is patterned. Immediately after being formed by the normal pressure CVD method, the BPSG film (6) is reflowed by a heat treatment at about 900 ° C. This reflow absorbs the steps of the base and smoothes the surface.

Next, a plurality of contact holes (7) are formed in the BPSG film (6) by photoetching. The formation of the contact hole (7) is performed by anisotropic etching using a dry method or two-stage etching of anisotropic etching and isotropic etching. In the figure, the B of a portion where the contact hole (7) is relatively close and surrounded by the contact hole (7) and separated from the surroundings.
The PSG film (6) is a BPSG film (6a) having a small volume. Conversely, the BPSG film (6) in a portion where the volume is increased due to the relative separation of the contact holes (7) is changed to a BPSG film (6).
SG film (6b). Then, when the silicon nitride film (6) is deposited by the LPCVD method, the BPSG film (6)
Of the contact hole (7) becomes gentle.

At this time, B during the deposition of the silicon nitride film (6)
The magnitude of the deformation of the PSG film (6) depends on the volume of the BPSG film (6). That is, if the volume is small, the deformation is small, and if the volume is large, the deformation is large. This is presumed to be because the amount of change per unit volume of the BPSG film (6) is almost constant. Therefore, a large amount of BPSG film (13
The change in the shape of the contact hole (7b) in which only a small amount of the BPSG film (6a) exists around the contact hole (7a) is extremely small with respect to the change in the shape of the contact hole (7a) in which the contact hole (b) exists. In the pattern design, the position of the contact hole (7) is designed in consideration of this phenomenon.

FIGS. 4 and 5 are views for explaining a second embodiment of the present invention. The silicon nitride film in the reflow process of the BPSG film (6) is commonly used as a dielectric thin film of a capacitor. First, the structure of the capacitor will be described. In the figure, the LOCOS oxide film (5) for element isolation is
It is formed on the surface of a semiconductor substrate or the surface of an epitaxial layer by a selective oxidation method. A lower electrode (12) serving as one electrode of the capacitive element is formed on the LOCOS oxide film (5) by a gate polysilicon material. A BPSG film (6) as an interlayer insulating film covers the LOCOS oxide film (5) and the lower electrode (12). The opening (13) formed in the BPSG film (6) exposes part of the surface of the lower electrode (12). A silicon nitride film (10) serving as a dielectric thin film of the capacitive element is deposited on the lower electrode (12) so as to cover the opening (13). The silicon nitride film (10) extends to the surface of the BPSG film (6) around the opening (13).

The upper electrode (1) serving as the other electrode of the capacitive element
4) is formed by the first-layer aluminum electrode wiring, and covers the silicon nitride film (10). Upper electrode (1
4) extends over the BPSG film (6) and is electrically connected to other circuit elements. A first contact hole (15) penetrating the BPSG film (6) is formed at a position surrounding the periphery of the silicon nitride film (10) except for a portion where the upper electrode (14) extends. An extraction electrode (16) of the lower electrode (12) is formed by the first-layer aluminum electrode wiring, and contacts the lower electrode (12) via the first contact hole (15). The extraction electrode (16) is a BPSG film (6)
And electrically connect to other circuit elements.

A dummy electrode (17), which is electrically separated from the lower electrode (12), is also arranged below the extending portion of the upper electrode (14) by a gate polysilicon material.
The second contact hole (18) is a dummy electrode (17).
It is formed on the upper BPSG film (6). Upper electrode (14)
Contacts the dummy electrode (17) via the second contact hole (18). Due to the fact that the dummy electrode (17) is separated from the lower electrode (12) and the first and second contact holes (15) and (18) are not continuous, the upper electrode (14) and the lower electrode ( 12) and electrical insulation is maintained.

First and second contact holes (15)
(18) almost completely surrounds the silicon nitride film (10). As a result, the BPSG film (6) is separated into a portion (6a) surrounding the periphery of the silicon nitride film (10) and a portion (6b) outside the portion. Therefore, the BPSG film (6a) surrounding the silicon nitride film (10) has the opening (13) and the first and second contact holes (15) (1).
8), the volume is reduced by the separation.

Then, at the stage of FIG. 1A, the lower electrode (12) of the capacitive element is formed on the LOCOS oxide film (5) by forming the gate electrode (2).
After the step (C), the opening (13) of the capacitive element and the first and second contact holes (15) (1) are formed in the step of FIG.
8), and a silicon nitride film (1) is formed in the step of FIG.
2) is deposited and selectively removed when removing the same, thereby forming a dielectric thin film of a capacitor.
In the step (C), the upper electrode (14) of the capacitive element is formed. According to this step, the silicon nitride film (10)
Can be shared with other steps, so that the steps can be simplified.

The reason why the first and second contact holes (15) and (18) are provided around the opening (13) is that
This is for alleviating the stress of the silicon nitride film (10) due to the deformation of the SG film (6). As described above, the magnitude of the deformation of the BPSG film (6) during the deposition of the silicon nitride film (10) depends on the volume of the BPSG film (6). . By providing first and second contact holes (15) and (18) around the opening (13) covered by the silicon nitride film (10), the volume of the BPSG film (6) around the opening (13) is reduced. And a change in the shape of the opening (13) is reduced. If the shape change is small, the opening (1
Since the stress applied to the silicon nitride film (10) deposited along the shape of 3) is small, the silicon nitride film (10)
Cracks can be prevented.

Although the present embodiment has been described with reference to a MOS integrated circuit, the present invention is not limited to a MOS integrated circuit, but is also applicable to a BIP integrated circuit or a BI-MOS integrated circuit. .

[0022]

As described above, according to the present invention, since the reflow process of the BPSG film (6) is performed by the deposition process of the silicon nitride film (10), there is an advantage that the process can be performed at a low temperature. Therefore, there is an advantage that variation in element characteristics can be reduced by suppressing the re-diffusion amount of the diffusion region.

Further, by combining the formation of the silicon nitride film (10) with the formation of the dielectric thin film of the capacitor, there is an advantage that the formation can be performed without complicating the manufacturing process.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a cross-sectional view showing a change in the shape of a BPSG film.

FIG. 4 is a plan view for explaining a second embodiment.

5A is a cross-sectional view taken along the line AA of FIG. 4, and FIG.

FIG. 6 is a cross-sectional view for explaining a conventional example.

FIG. 7 is a cross-sectional view illustrating a conventional example.

Claims (3)

(57) [Claims] 1. A forming an insulating film on a semiconductor substrate, Nada et a surface of the insulating film by applying a heat treatment to the insulating film
A step of the or contact holes in the insulating film - forming a le, by depositing a silicon nitride film on the entire surface, the heat treatment at the time of deposition
Wherein the step of gently the shape of the contact hole, and removing the silicon nitride film, a manufacturing method of a semiconductor integrated circuit, characterized by comprising a step of forming an electrode wiring on the contact hole Ri. Wherein deposition of the silicon nitride film, the insulating
2. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the step involves a heat treatment at a temperature lower than the flow temperature of the film . 3. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein said silicon nitride film is partially left as a dielectric thin film of a capacitor.