JPH02308619A - Signal delay device - Google Patents

Abstract

PURPOSE:To improve the delay accuracy by retarding a digital signal synchronously with the leading edge and trailing edge of a clock so as to apply logic processing. CONSTITUTION:A digital input signal 1 is retarded with 1st and 2nd positive delay devices 3, 5 synchronously with the leading edge of a clock 2 and retarded with 1st and 2nd negative delay devices 7, 8 synchronously with the trailing edge of the clock 2. Then the output of the delay devices 5, 9 is processed by an AND device 11 and the delay time is controlled with an accuracy of a half period of the clock to improve the delay accuracy within one period of the clock.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal delay device for delaying a digital signal in synchronization with a clock input.

Conventional technology A conventional signal delay device will be explained below.

FIG. 3 is a block diagram of a conventional signal delay device. Third
In the figure, 21 is a digital input signal, 22 is a clock, and a first delay device 23 is a digital input signal 21.
is delayed in synchronization with the rising edge of the clock 22. The second delay device 25 delays the first digital output signal 24 delayed by the first delay device 23 in synchronization with the rising edge of the clock 22, and causes the second digital output signal 26 to be delayed.
Output. FIG. 4 is a timing chart showing the operation of FIG. 3.

The operation of the signal delay device configured in this way will be described below. First, the digital input signal 21 is delayed by the first delay device 23 in synchronization with the rising edge of the clock 22, and is output as the first digital output signal 24. The first digital output signal 24 is delayed by a second delay device 25 in synchronization with the rising edge of the clock 22, and the digital input signal 21 changes the period of the clock by an operation of 0 or more which is output as a second digital output signal 26. Assuming t seconds, the signal is delayed from 2 seconds to 2 seconds, and is output as the second digital output signal 26 from the signal delay device.

This delay time will be explained using FIG. 4. The digital input signal (A) shows the case where the digital input signal falls immediately after the clock rises from L to H. In this case, the first digital output signal 24 output from the first delay device 23 is output with a delay of t seconds compared to the input. The second digital output signal 26 output from the second delay device is output with a further delay of t seconds, so the delay time due to the signal delay device becomes 2 seconds. Further, the digital input signal (B) shows the case where the digital input signal falls immediately before the clock rises from L to H. In this case, the first digital output signal 24 output from the first delay device 23 is output without delay. Since the second digital output signal 26 output from the second delay device 25 is output with a delay of t seconds, the delay time due to the signal delay device is t seconds.Since it is greater than 0, the delay time in this conventional example is 2 seconds from t seconds. become.

Problems to be Solved by the Invention However, in the conventional configuration described above, the ambiguity of the delay time is equivalent to one clock period (in seconds), and the problem is that the accuracy of the delay time cannot be shortened to within one clock period. It had

The present invention is intended to solve the above-mentioned conventional problems, and aims to provide a signal delay device that can control delay time with an accuracy of half a clock cycle.

Means for Solving the Problems In order to solve the above problems, the signal delay device of the present invention includes:
A delay device that delays a digital signal in synchronization with the rising edge of a clock, a delay device that delays a digital signal in synchronization with a falling edge of a clock, and a logical sum or logic of the digital output signals of the two types of delay devices. This configuration includes a logical summation device or a logical multiplier for multiplication.

Effect: With the above configuration, it is possible to realize an excellent signal delay device that can control the delay time with an accuracy of half a clock cycle and can shorten the accuracy to within one clock cycle.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a signal delay device showing an embodiment of the present invention. In FIG. 1, 1 is a digital input signal, 2 is a clock, and the first positive polarity delay device 3 delays the digital input signal 1 in synchronization with the rising edge of the clock 2.

A second positive-polarity delay device 5 delays the first positive-polarity delayed digital output signal 4 delayed by the first positive-polarity delay device 3 in synchronization with the rising edge of the clock 2, and outputs a second positive-polarity delayed digital output signal. Outputs signal 6. First negative delay device 7
delays the digital input signal 1 in synchronization with the falling edge of the clock 2. A second negative-polarity delay device 9 delays the first negative-polarity delayed digital output signal 8 delayed by the first negative-polarity delay device 7 in synchronization with the rising edge of the clock 2, and outputs a second negative-polarity delayed digital output signal. Outputs signal 10. Reference numeral 11 denotes an AND device for ANDing the second positive-polarity delayed digital output signal 6 and the second negative-polarity delayed digital output signal 10, and outputs a digital output signal 12. FIG. 2 is a timing chart showing the operation of FIG. 1.

The operation of the signal delay device of this embodiment configured as described above will be described below. First, the digital input signal 1 is delayed by the first positive delay device 3 in synchronization with the rising edge of the clock 2, and is output as the first positive delayed digital output signal 4.

The first positive-polarity delayed digital output signal 4 is delayed by a second positive-polarity delayer 5 in synchronization with the rising edge of the clock 2, and is output as a second positive-polarity delayed digital output signal 6. Further, the digital input signal 1 is delayed by the first negative polarity delay device 7 in synchronization with the falling edge of the tarlock 2,
The first negative polarity delayed digital output signal 8 is output.

The first negative delayed digital output signal 8 is delayed by a second negative delay device 9 in synchronization with the falling edge of the clock 2, and is output as a second negative delayed digital output signal 10. The second positive delayed digital output signal 6 and the second negative delayed digital output signal 10 enter an AND gate 11 . Since the AND gate 11 is falling except when both the two signals are rising, when the digital input signal 1 falls, the second positive polarity delay signal 6 and the second negative polarity delay signal The logical multiplier 11 falls at the timing of the signal that falls earlier within 10 degrees.Due to the operation of 0 or more, the digital input signal 1 changes from t seconds to 1.
5 is delayed by seconds and output from the signal delay device as the output of the AND gate 11.

This delay time will be explained using FIG. 2. The digital input signal (A) shows the case where the digital input signal falls immediately after the tarok rises from L to H. The digital input signal (B) shows the case where the digital input signal falls immediately before the clock rises from L to H. The digital input signal (C) shows the case where the digital input signal falls immediately before the clock falls from H to L. The digital input signal (D) shows the case where the digital input signal falls immediately after the clock falls from T to L. No matter which timing of the digital input signal (A), digital input signal (B), digital input signal (C), or digital input signal (D) enters the first positive polarity delay device 3, the first positive polarity delay The digital output signal 4 falls at the rising edge of the same clock.

A second positive polarity delay device 5 delays the first positive polarity delayed digital output signal 4 by t seconds and outputs a second positive polarity delayed digital output signal 6. In the first negative polarity delay device 7, the digital input signal (A) and the digital input signal (C) are outputted as a first negative polarity delayed digital output signal (8'), and the digital input signal (B) and the digital input signal ( D) is output as a first negative-polarity delayed digital output signal (8'). The second negative polarity delay device 9 supplies the first negative polarity delayed digital output signal (8'
) is delayed for t seconds, and the second negative polarity delayed digital output signal (1
0') is output. Therefore, the first negative delayed digital output signal (8') is delayed by t seconds and output as the second negative delayed digital output signal (10'), and the first negative delayed digital output signal (8'') is delayed by t seconds. seconds and is output as a second negative-polarity delayed digital output signal (10''). In the case of the digital input signal (A) and the digital input signal (C), the AND output of the AND device 11 is the second positive polarity delayed digital output signal 6 and the second negative polarity delayed digital output signal (10
'), and the second negative polarity delayed digital output signal (1
An AND output (12') is output at the timing when 0') falls. Therefore, there is a delay of 1.5 seconds from t seconds from the digital input signal to the AND output. In addition, in the case of digital input signal (B) and digital input signal (D), the second
The positive polarity delayed digital output signal 6 and the second negative polarity delayed digital output signal (io') are logically ANDed, and the logical product output (12
Therefore, there is a delay of 1.5 seconds from t seconds from the digital input signal to the AND output.

As described above, according to the present embodiment, there is provided a delay device that delays a digital signal in synchronization with the rising edge of a clock, a delay device that delays a digital signal in synchronization with the falling edge of the clock, and the two types of delays. By using the configuration with an AND device that ANDs the digital output signals of the device, it is possible to control the delay time of the digital signal from t seconds to 1.5 seconds and the ambiguous delay time to an accuracy of half a clock cycle. can.

Note that in this embodiment, the number of stages of the delay device is two, but the number of stages is one.
In addition, although the case where the delay of the falling edge of the digital input signal is controlled is shown,
It is also possible to control the delay of the rising edge of the digital input signal by using a logical adder instead of a logical product.

Effects of the Invention As described above, according to the present invention, there are provided a delay device for delaying a digital signal in synchronization with the rising edge of the tarock, a delay device for delaying the digital signal in synchronization with the falling edge of the clock, and the aforementioned two types. An excellent signal delay device that can control the delay time of a digital signal with half-cycle accuracy can be realized by configuring it with an AND or OR device that ANDs or ORs the digital output signals of the delay device. It is something.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a signal delay device according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of FIG. 1, FIG. 3 is a block diagram of a conventional signal delay device, and FIG. 4 is a block diagram of a conventional signal delay device. 3
5 is a timing chart showing the operation shown in the figure. 1...Digital input signal, 2...Clock, 3...
- First positive polarity delay device, 4... First positive polarity delayed digital output signal, 5... Second positive polarity delay device, 6... Second positive polarity delayed digital output signal, 7...・First negative polarity delay device, 8...First negative polarity delayed digital output signal, 9
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Claims (1)

[Claims] 1. A first delay device that receives a digital input signal and a clock and delays the digital input signal in synchronization with the rising edge of the clock; and a first delay device that delays the digital input signal in synchronization with the falling edge of the clock. a second delay device that performs a logical sum or a logical product of the digital output signals of the first and second delay devices; A signal delay device configured to delay edges.