JPS6074814A - Delay circuit - Google Patents

Abstract

PURPOSE:To miniaturize the circuit constitution and also to improve the accuracy of delay time by using two shift registers which work at the rise and fall of a clock pulse and obtaining an OR and an AND of shift output signals of each stage. CONSTITUTION:The shift clock and input signal are applied to shift registers 1 and 2 from input terminals 3 and 5 respectively. The shift signal outputs of FFs of A2 and B2, A3 and B3 and A4 and B4 of the registers 1 and 2 are delivered to P2-P4 after an OR obtained through OR gates OR2-OR4 and then to N2- N4 after an AND obtained by AND gates AND2-AND4 respectively. If the register 1 works at the rise of the shift clock, for example, the register 2 works at the fall of the shift clock respectively by a buffer inverter 4. In such a constitution, a delay circuit can be miniaturized with conversion into an LSI and furthermore the accuracy of the delay time can be improved up to 1/2 cycle of the shift clock of the using shift register.

Description

[Detailed description of the invention] (a) Technical field of the invention The present invention relates to a delay circuit using a shift register.

(b) Background of the Technology In electronic circuits that handle digital signals, temporal variations in signal propagation are unavoidable, as can be seen in the signal transfer between the channel device and input/output device of a computer, for example.
A delay circuit is used to correct this.

Electronic circuits such as those mentioned above have traditionally been equipped with induction wires and capacitors (
An LC delay line with an intermediate tag consisting of Q has a total of f! A
The extension time is from several tens of nanoseconds to several hundred nanoseconds, and the tap delay time is from several nanoseconds to several tens of nanoseconds.However, integrated circuits (hereinafter referred to as ICs) have progressed. In recent electronic circuits, the dimensions of LC delay lines are large, creating problems in terms of mounting space.

In electronic circuits, although not specifically called delay circuits, it is necessary to improve accuracy in order to replace shift registers in circuits with delay functions in place of wire extensions.

(C)' Prior Art and Problems In recent years, electronic circuits have been using large-scale integrated circuits (hereinafter abbreviated as LSI), which has resulted in a decrease in the number of parts used in devices and a reduction in the size of devices.

However, since a delay circuit using an LC delay line has a built-in induction fs ring, it is difficult to integrate it into an LSI, and a large space must be allocated to the delay circuit, which has been a major obstacle to miniaturizing the device.

A shift register having a delay function can be made into an LS1, and if this can be utilized in a delay circuit, the problem of miniaturization can be solved at once, but the conventional technology has the following accuracy problems.

FIG. 1 shows a block diagram of a conventional delay circuit using a shift register, and FIG. 2 shows a time chart of delay time formation by the delay circuit.

In FIG. 1, 1 is a shift register in which a plurality of flip-flops (hereinafter abbreviated as FF) are connected in series, and the FFs are AI, A2 . A case of 4 pieces, A3° and A4, is shown.

A shift clock is input to the shift register 1 from 3, an input signal is input from 5, and a shift signal is output from each FF. The delay time is obtained as the time from the rise or fall of the input signal to the rise or fall of the shift signal, but here it will be explained as the time from the rise of the input signal to the rise of the shift signal.

FIG. 2 shows a time chart of shift signals output from each FF of the shift register 1 on the time axis of the shift clock. It is assumed that each FF operates at the rising edge of the shift clock.

In Figure 2, when considering the timing of the rising edge of the input signal and the rising edge of the shift clock, if we consider cases where the rising edge of the input signal is immediately before and immediately after the shift clock, all such timings can be calculated. within this range.

The case of input signal (1) in FIG. 2 shows the former case, and the case of input signal (2) shows the latter case.

In FIG. 2, there are four types of shift signals for the input signals (1) and (2), but the rising edge of the input signal All is close to the rising edge of the All signal, so there are cases where it is not possible to take a delay time. Therefore, as shown in FIG. 1, the shift signal output for determining the delay time is taken out as 62.63.64 from the A2 output of the second stage of FF. Input signals (1) and (2) from output terminal 62
), the shift signals A21 and A22 are compared in FIG. 2, and it can be seen that there is a difference of one period T of the clock signal between the delay times t and r of each. This difference T occurs similarly at the other output terminals 63 and 64, and this is the accuracy of the delay circuit shown in FIG.

The above explanation uses an example of an FF that turns on and off with the delay time from the rising edge of the input signal or the rising edge of the shift clock, but the result is the same even if this function is operated at each falling edge, and the accuracy of the delay time is as described above. It can be suppressed by T. That is, in the prior art, a delay circuit using a shift register cannot improve accuracy beyond the 77 clock cycle of the shift register. The cycle of the shift clock cannot be arbitrarily shortened due to restrictions on the operating speed of the elements used, and there is a problem in that the cycle that can be realized at present cannot reach the accuracy of the LC delay line.

(d) Purpose of the Invention In view of the problems of the prior art described above, the present invention uses a shift register in a delay circuit to reduce the size of the delay circuit by making it into an LSI. The purpose is to shorten and improve the clock cycle.

(e) Structure of the Invention The present invention provides a delay circuit that delays an input signal by a predetermined delay time, which includes a clock signal having a cycle sufficiently short with respect to the delay time, and a first shift register that operates at the rising edge of the clock signal. and a second shift register that operates at the falling edge of the clock signal, and means for forming a logical sum and a logical product of the outputs of the second and subsequent n stages of the first and second shift registers, The delay circuit is input to the first and M2 shift registers and performs a shift operation in response to the clock signal, and detects the output signals of the logical sum and logical product. The precision of the delay time can be reduced to 1/2 of the period of the shift clock of the shift register, and the above object is fully achieved.

(f) Embodiment of the Invention Fig. 3 shows a block diagram of an embodiment of the circuit configuration of a delay circuit using a shift register according to the invention, and Fig. 4 (
Figures a), (b), (c), and (d) show time charts of delay time formation by the delay circuit embodiments of the present invention for input signals input at four different timings with respect to the shift clock.

In FIG. 3, 1 is four FFs Al, A2. A3゜A
4 shift registers, 2 is 4 FF Bl.

B2. B3. B4 shows a shift register, 3 is the input end of the shift clock with a duty factor of 50%,
4 indicates a buffer inverter that inputs the shift clock into shift registers 1 and 2 with opposite phases, and 5 indicates an input terminal of an input signal A2 and B2 of shift registers 1 and 2. The shift signal outputs of the FFs A3, B3°A4, and B4 are logically summed by OR gates OR2, 0R3, and OR4, respectively, and outputted as B2°B3. Output to B4 and AND gate A
ND2. AND3゜AND4 performs logical product and N2
．． N3. Output to N4. These are P2. P3. P4 and N2. N3. The N4 signal has delay time information,
Take this out and use it.

Although the delay circuit shown in FIG. 3 can form a delay time from the rising or falling edge of an input signal, this explanation will take as an example the case where the delay time is formed from the rising edge. Shift registers 1 and 2 have the same function, but due to the buffer inverter 4, for example, if shift register 1 operates on the rising edge of the shift clock, shift register 2 operates on the falling edge of the shift clock. As in Figure 2, the outputs of the FFs in each stage of shift registers 1 and 2 are shown with A and B, with the period being T and the shift clock of duty factor 50 being the time axis. The outputs of the logical sum and logical product are shown with P and N attached.

As in Figure 2, the timing of the rising edge of the input signal and the rising and falling edges of the shift clock must be taken into account when the rising edge of the input signal is before and after the rising edge of the shift clock, and when it is before and after the falling edge of the shift clock. No. In the former case, (a) and (6) in FIG. 4 correspond, and in the latter case, (c) and (d) in FIG. 4 correspond.

FIG. 4(a), (b)-(c), (Comparing P and N of d3, the delay time from the rise of each input signal is as shown in the following table.

From the above table, there are six types of delay times in this example including P and N, but the accuracy is 1/2T in all cases.

The above explanation has been given by taking as an example the delay time from the rise of the input signal, but the delay time can be similarly calculated from the fall of the input signal, and in this case as well, the precision of the delay time is 1/2T. That is, the present invention uses two shift registers that operate on the rising and falling edges of a clock pulse, and obtains the delay time from the logical sum and logical product of the shift output signals of the FFs in each stage of the shift register. As a result, the accuracy of delay time can be improved to 1/2T, twice that of the conventional method.

(g) Effects of the Invention According to the present invention, the delay circuit can be made smaller by integrating it into an LSI, and the period I of the shift clock of the shift register used can be reduced.
A, high precision can be achieved, and it has an extremely large effect on improving the mounting space of electronic devices and increasing reliability.

[Brief explanation of drawings]

Fig. 1 shows a block diagram of a delay circuit using a conventional shift register, Fig. 2 shows a time chart in which the delay circuit of Fig. 1 forms a delay time, and Fig. 3 shows a shift register of the present invention. An example of the delay circuit used is shown in a block diagram, and FIG. 4 shows a time chart in which the delay circuit of FIG. 3 forms delay times for four types of signal inputs (a),
Shown in (b), (c) and 1d).

Claims (1)

[Claims] In a delay circuit that delays an input signal by a predetermined delay time, a clock signal having a sufficiently short period relative to the delay time, a first shift register that operates at the rising edge of the clock signal, and a clock signal that operates at the falling edge of the clock signal are used. comprising means for forming a logical sum and a logical product of an operating second shift register and the outputs of the second and subsequent n stages of the first and second shift registers, the input signal being input to the first and second shift registers; A delay circuit characterized in that it performs a shift operation in synchronization with an input signal and detects an output signal of the logical sum and the logical product.