JPS62182824A - Reading circuit - Google Patents

Abstract

PURPOSE:To shorten the time during which the value of an internal register which changes synchronously with an internal clock after the asynchronous read signal is enabled and then the value of said register is delivered to a bus, by providing a latch circuit, a timing control circuit and a delay circuit. CONSTITUTION:A timing control circuit 14 synchronizes an asynchronous read signal (a) for each half cycle of an internal clock (c) and produces an internal synchronous read signal (b). This signal (b) synchronizes the signal (a) after this signal is enabled and in response to one of both fall and rise edges of the clock (c) that emerges first. While the register value (e) changes synchronously with a delay clock (d). This clock (d) delays the clock (c) and therefore the value (e) is latched by a latch circuit 13 by the signal (b) even though the signal (b) is synchronous with the fall or rise of the clock (c). Then a signal (f) is outputted to a bus 12 from the circuit 13.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a readout circuit used in an OPU or the like.

BACKGROUND OF THE INVENTION FIG. 3 is a schematic block diagram showing an example of a conventional readout circuit.

This readout circuit includes a timing control circuit 1 which inputs an asynchronous read signal g and an internal clock i and generates an internal synchronous read signal synchronized with the internal clock I, and an internal timing control circuit 1 which changes the value in synchronization with the internal clock i. register 2
and a latch circuit 3 that latches the value j of the internal register 2 in accordance with an internal synchronous read signal, and the latch circuit 3 outputs the value k to the path 4 to perform reading.

Problems to be Solved by the Invention However, in such a read circuit, the value j of the internal register 2 is not read after the asynchronous read signal g is enabled.
It may take one period of the maximum internal clock I until the signal is latched and output to the path 4, which poses a problem that reading the internal register 2 using the asynchronous read signal g cannot be performed at high speed. This occurs for the following reasons.

That is, as shown in FIG. 4, the asynchronous lead g is
ON”, generates an internal synchronous read signal 11 synchronized with the rising edge of the internal clock i, latches the value j of the internal register that changes in synchronization with the falling edge of the internal clock 1, and latches it according to the internal synchronous read signal. This is because the value 1 was output to the path.

The present invention has been made in view of the above-mentioned problems.The present invention has been made in view of the above-mentioned problems. It is an object of the present invention to provide a readout circuit that can shorten the time.

Means for Solving the Problems In order to achieve the above object, the present invention includes a latch circuit that latches the output value of an internal register that operates in synchronization with a predetermined clock signal and outputs it to a path, and an asynchronous read signal and an internal clock. A timing control circuit that inputs a signal and outputs a latch circuit timing signal, inputs an internal clock signal, delays this signal by a time less than half a cycle,
The device is characterized in that it includes a delay circuit that outputs a delayed clock signal to an internal register.

Operation With the above configuration, the value of the internal register is changed by the delayed clock signal, while the asynchronous read signal is synchronized with the rising or falling edge of the internal clock, and the value of the internal register is changed according to the internal synchronous read signal created thereby. This value is latched by the latch circuit, and this value is output from the latch circuit to the path.

Embodiment FIG. 1 is a schematic block diagram showing a readout circuit according to an embodiment of the present invention.

This readout circuit includes an internal register 11 that operates in synchronization with a predetermined clock signal, a latch circuit 13 that latches the output value of this internal register 11 and outputs it to a path 12, and an asynchronous read signal a and an internal clock C. The internal clock C is input to the timing control circuit 14 which outputs the latch timing signal to the latch circuit 13, and is delayed by a time less than half a period to generate the delayed clock (hereinafter referred to as
d (referred to as a delay clock) to the internal register 11. Internal register 11 outputs register value e in accordance with delayed clock d. This register value e is latched by a latch circuit 13, and is output as a signal f to a path 12 in response to an internal synchronous read signal.

The operation of the readout circuit configured as above will be explained with reference to FIGS. 2(A) and 2(B).

First, the timing control circuit 14 synchronizes the asynchronous read signal a every half period of the internal clock C to generate an internal synchronous read signal S. This internal synchronous read signal starts when the asynchronous read signal a becomes enabled, and then the internal clock C
The asynchronous read signal a is synchronized in accordance with the edge which appears earlier among the falling and rising edge of the signal.

On the other hand, the register value e changes in synchronization with the delayed clock d. Since this delayed clock d delays the internal clock C, the internal synchronous read signal l)
Regardless of whether the edge is synchronized with the falling edge of
It is latched to 3. Then, a signal f is sent from the latch circuit 13.
is output to path 12. Here, the delay clock d delays the internal clock C by a time less than half a cycle,
As a result, the time t from when the asynchronous read signal a is enabled until the value of the internal register 11 is latched and output to the path 12 can be suppressed to a maximum of half the period of the internal clock C.

Effects of the Invention As is clear from the above description, according to the present invention, a clock delay circuit is provided, and while the value of an internal register is changed in synchronization with a delayed internal clock generated by the clock delay circuit, half of the internal clock is The asynchronous read signal is synchronized with the period, thereby creating an internal synchronous read signal, and the value of the internal register is latched according to this internal synchronous read signal, and the value of the internal register is latched after the asynchronous read signal is enabled. The time required for output to the path can be reduced to at most half the cycle of the internal clock.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing a readout circuit according to an embodiment of the present invention, FIGS. 2A and 2B are signal waveform diagrams of the readout circuit, and FIG. 3 is an example of a conventional readout circuit. The schematic block diagram and FIG. 4 are signal waveform diagrams of the readout circuit. 11...Internal register, 12...Path, 13...
Latch circuit, 14... Timing control circuit, 15...
・Delay circuit. Name of agent: Patent attorney Satoshi Nakao et al. 1 Tatsutsu 2
figure

Claims (1)

[Claims] An internal register that operates in synchronization with a predetermined clock signal;
a latch circuit that latches the output value of this internal register and outputs it to the path; a timing control circuit that inputs an asynchronous read signal and an internal clock signal and outputs a latch timing signal to the latch circuit; a delay circuit that inputs an input clock signal, delays this signal by a time less than half a cycle, and outputs the delayed clock signal to the internal register.