JPH02304929A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02304929A JPH02304929A JP1125825A JP12582589A JPH02304929A JP H02304929 A JPH02304929 A JP H02304929A JP 1125825 A JP1125825 A JP 1125825A JP 12582589 A JP12582589 A JP 12582589A JP H02304929 A JPH02304929 A JP H02304929A
- Authority
- JP
- Japan
- Prior art keywords
- film
- bump
- photo
- resist
- bump electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000010408 film Substances 0.000 claims abstract description 44
- 239000010931 gold Substances 0.000 claims abstract description 37
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 17
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052737 gold Inorganic materials 0.000 claims abstract description 13
- 238000007747 plating Methods 0.000 claims abstract description 10
- 239000010409 thin film Substances 0.000 claims abstract description 8
- 238000001039 wet etching Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000010884 ion-beam technique Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 2
- 230000002265 prevention Effects 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 abstract description 6
- 230000001070 adhesive effect Effects 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体装置の製造方法に関し、特に外部接続端
子であるｔｒｉ用金バンプを有する半導体装置に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device having tri gold bumps serving as external connection terminals.
［従来の技術］
従来、半導体装置の電極用金バンプの製造方法に関して
は数多くの提案がなされ、改良が加えられている。第２
図は、従来の電極用金バンプ製造工程の断面図である。[Prior Art] Conventionally, many proposals have been made and improvements have been made regarding methods of manufacturing gold bumps for electrodes of semiconductor devices. Second
The figure is a cross-sectional view of a conventional gold bump manufacturing process for electrodes.
従来は第２図に示すように、集積回路全面にＴｉ膜２４
、Ｐｔ膜２５から成る薄膜層を形成した後、ＡＩ２電極
パッド２２上にフォトレジスト膜２６を形成して、Ｐｔ
膜２５をウェットエツチングにより除去をする、前記フ
ォトレジスト１１！２６を剥離除去した後、バターニン
グされたＰｔ膜２５上に開口部をもつフォトレジスト膜
２７を形成する。前記フォトレジスト膜２７をマスクと
してＡｕメッキによりバンプ電極２８を形成した後、前
記フォトレジスト膜２７を剥離除去する。最期に前記Ｐ
ｔ膜２５をマスクとしてＴｉ膜２４をウェットエツチン
グにより除去をしていた。このような従来の製造方法で
は以下に示す欠点があった。Conventionally, as shown in FIG. 2, a Ti film 24 was deposited on the entire surface of the integrated circuit.
, after forming a thin film layer consisting of a Pt film 25, a photoresist film 26 is formed on the AI2 electrode pad 22, and a Pt film 25 is formed.
The film 25 is removed by wet etching. After the photoresist 11!26 is peeled off and removed, a photoresist film 27 having an opening is formed on the patterned Pt film 25. After forming bump electrodes 28 by Au plating using the photoresist film 27 as a mask, the photoresist film 27 is peeled off. At the end, the above P
The Ti film 24 was removed by wet etching using the T film 25 as a mask. Such conventional manufacturing methods have the following drawbacks.
まず、Ｐｔ１ｌｌ１２５をエツチングする時にフォトレ
ジスト膜２６を使用する為に、Ａｕメッキ時のフォト工
程の他にフォト工程を必要とすることである。First, since the photoresist film 26 is used when etching the Pt1ll125, a photo process is required in addition to the photo process used during Au plating.
また、Ａｕメッキにより形成されるバンプ電極２８は、
異種金属であるＰｔ膜２５に接着させねばならない為、
接着強度が低く、半導体装置を実装した際の信頼性に欠
けるという問題を生じていた。Moreover, the bump electrode 28 formed by Au plating is
Since it must be bonded to the Pt film 25, which is a different metal,
The adhesive strength was low, causing a problem of lack of reliability when semiconductor devices were mounted.
その上、バンプ電極２８の表面をエツチングする工程が
無い為、メッキフォトレジスト膜２７の残渣の付着など
で、半導体装置を実装した際に、大きな電気抵抗を生じ
るという問題もあった６［発明が解決しようとする課題
１
本発明は、前記従来技術の欠点を解決しようとするもの
であり、接着強度が高く、低い電気抵抗の金バンプ電極
であるばかりか、簡便で高い生産性をもつ工程で構成さ
れる半導体装置の製造方法を提供することにある。Furthermore, since there is no step of etching the surface of the bump electrode 28, there is a problem that a large electrical resistance is generated when a semiconductor device is mounted due to the adhesion of residues of the plating photoresist film 27. Problem to be Solved 1 The present invention attempts to solve the above-mentioned drawbacks of the prior art, and provides not only a gold bump electrode with high adhesive strength and low electrical resistance, but also a process that is simple and highly productive. An object of the present invention is to provide a method for manufacturing a semiconductor device comprising the following configurations.
集積回路の電極パッド上および絶縁膜上に、金バンプ電
極を製造する方法において
（１）集積回路全面に、密着層としてのＴｉ、相互拡散
防止バリアとしてのＰｔ、電解メッキ下地電極としての
Ａｕ、から成る金属薄膜層を順次連続で形成する工程
（２）前記金属膜上に開口部をもつフォトレジスト膜を
形成する工程
（３）前記フォトレジスト膜をマスクとしてＡｕメッキ
を行ないバンプ電極を形成し、フォトレジストを剥離除
去する工程
（４）ウェットエツチングにより、Ａｕ薄膜の除去及び
バンプ表面をわずかに除去する工程（５）イオンビーム
エツチングにより、バンプ電極をマスク材としてＰｔ薄
膜、Ｔｉ薄膜を順次除去する工程
から成ることを特徴とする半導体装置の製造方法。In a method for manufacturing gold bump electrodes on electrode pads and insulating films of integrated circuits, (1) Ti as an adhesion layer, Pt as a mutual diffusion prevention barrier, Au as an electrolytic plating base electrode, (2) Forming a photoresist film having openings on the metal film (3) Using the photoresist film as a mask, perform Au plating to form bump electrodes. , Step of peeling off the photoresist (4) Step of removing the Au thin film and slightly removing the bump surface by wet etching (5) Step of removing the Pt thin film and Ti thin film sequentially by ion beam etching using the bump electrode as a mask material 1. A method for manufacturing a semiconductor device, comprising the steps of:
以下に１本発明の実施例について、図面を参照して説明
する。An embodiment of the present invention will be described below with reference to the drawings.
第１図（ａ）〜（ｆ）は本発明の詳細な説明するための
工程順を示した断面図である。FIGS. 1(a) to 1(f) are cross-sectional views showing the order of steps for explaining the present invention in detail.
第１図（ｂ）に示すように、拡散、配線、絶縁膜工程の
終了した集積回路上のパッシベーション！１１３及びア
ルミ電極パッド１２の上に密着層として０．１μｍのＴ
ｉ膜１４と拡散バリア層として０２μｍのＰｔ１ｌ１５
と、メッキ下地層として０．１ｕｍのＡｕ１ｌｉ１８を
順次連続的にスパッタ法により形成する。As shown in Figure 1(b), passivation on the integrated circuit after diffusion, wiring, and insulating film processes has been completed! 113 and the aluminum electrode pad 12 as an adhesive layer with a thickness of 0.1 μm.
02μm Pt1l15 as i film 14 and diffusion barrier layer
Then, as a plating base layer, 0.1 um of Au1li18 is sequentially and continuously formed by sputtering.
次に第１図（ｃ）に示すように、前記金属膜上に、バン
プ電極形成用の開口部を形成するようにフォトレジスト
月莫１７をもうける。Next, as shown in FIG. 1(c), a photoresist layer 17 is formed on the metal film to form an opening for forming a bump electrode.
次に第１図（ｄ）に示すように、フォトレジスト開口部
に電解金メッキにより１５〜３０μｍ厚のＡｕバンプ１
８を形成し、前記フォトレジスト膜１７を剥離液または
酸素プラズマ法により除去する。Next, as shown in FIG. 1(d), Au bumps 1 with a thickness of 15 to 30 μm are formed on the photoresist openings by electrolytic gold plating.
8 is formed, and the photoresist film 17 is removed using a stripping solution or an oxygen plasma method.
次に第１図（ｅ）に示すように、Ａｕエツチング液によ
り、前記Ａｕバンプ１８をマスク材として前記Ａｕ膜１
６を除去する。この時、Ａｕバンプ１８の表面も、０１
μｍ除去されるので、フォトレジスト残渣等の汚れを完
全に除去することができる。Next, as shown in FIG. 1(e), the Au film 1 is etched using an Au etching solution using the Au bumps 18 as a mask material.
Remove 6. At this time, the surface of the Au bump 18 is also 01
Since .mu.m is removed, stains such as photoresist residue can be completely removed.
次に第１図（ｆ）に示すように、イオンビームエツチン
グ法により、前記Ａｕバンプ１８をマスク材として前記
Ｐｔ１ｉ１５及び前記Ｔｉ膜１４を順次エツチング除去
する。この時、Ａｕバンプ１８の上面つまり実装される
面は約１μｍエツチングされるので、汚れは完全に除去
される。Next, as shown in FIG. 1(f), the Pt1i 15 and the Ti film 14 are sequentially etched away using the Au bump 18 as a mask material by ion beam etching. At this time, the upper surface of the Au bump 18, that is, the surface on which it is mounted, is etched by about 1 μm, so that the dirt is completely removed.
以下の工程により、金バンプ電極が集積回路上に形成さ
れる。形成された金バンプは前記説明のように、接着強
度が高く、低い電気抵抗であるばかりか、スパッタ１回
、フォト１回という簡便な工程で、高い生産性をもつ製
造方法により形成されるものである。Gold bump electrodes are formed on the integrated circuit through the following steps. As explained above, the formed gold bumps not only have high adhesive strength and low electrical resistance, but are also formed by a manufacturing method with high productivity using a simple process of one sputtering and one photo process. It is.
〔発明の効果］
以上説明したように本発明の製造方法により、接着強度
が高く、低い電気抵抗の高い信頼性をもつ金バンプ電極
であるばかりか、簡便で高い生産性をもつ工程で半導体
装置を提供することができた。[Effects of the Invention] As explained above, the manufacturing method of the present invention not only provides highly reliable gold bump electrodes with high adhesive strength and low electrical resistance, but also manufactures semiconductor devices using a simple and highly productive process. were able to provide the following.
第１図（ａ）〜（ｆ）は、本発明の実施例による半導体
装置の製造方法の断面図。
第２図（ａ）〜（ｇ）は、従来技術による半導体装置の
製造方法の断面図。
１１・・・集積回路基板
１２・・・アルミ電極パッド
１３・・・パッシベーション膜
１４・・・Ｔｉ膜
１５・・・Ｐｔ膜
１６・・・Ａｕ膜
１７・・・フォトレジスト膜
１８・・・Ａｕバンプ
２１・・・集積回路基板
２２・・・アルミ電極パッド
２３・・・パッシベーション膜
２４・・・Ｔｉ膜
２５・・・Ｐｔ膜
２６・・・フォトレジスト膜
２７・・・フォトレジスト膜
２８・・・Ａｕバンプ
以上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴 木 喜三部（他１名）算１（因FIGS. 1(a) to 1(f) are cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 2(a) to 2(g) are cross-sectional views of a method of manufacturing a semiconductor device according to the prior art. 11... Integrated circuit board 12... Aluminum electrode pad 13... Passivation film 14... Ti film 15... Pt film 16... Au film 17... Photoresist film 18... Au Bump 21... Integrated circuit board 22... Aluminum electrode pad 23... Passivation film 24... Ti film 25... Pt film 26... Photoresist film 27... Photoresist film 28...・Applicant for Au bumps and above Seiko Epson Co., Ltd. agent Patent attorney Kizobe Suzuki (and 1 other person)
Claims (1)
極を製造する方法において （ａ）集積回路全面に、密着層としてのＴｉ、相互拡散
防止バリアとしてのＰｔ、電解メッキ下地電極としての
Ａｕ、から成る金属薄膜層を順次連続で形成する工程 （ｂ）前記金属膜上に開口部をもつフォトレジスト膜を
形成する工程 （ｃ）前記フォトレジスト膜をマスクとしてＡｕメッキ
を行ないバンプ電極を形成し、フォトレジストを剥離除
去する工程 （ｄ）ウェットエッチングにより、Ａｕ薄膜の除去及び
バンプ表面をわずかに除去する工程 （ｅ）イオンビームエッチングにより、バンプ電極をマ
スク材としてＰｔ薄膜、Ｔｉ薄膜を順次除去する工程 から成ることを特徴とする半導体装置の製造方法。[Claims] A method for manufacturing a gold bump electrode on an electrode pad and an insulating film of an integrated circuit: (a) Ti as an adhesion layer, Pt as a mutual diffusion prevention barrier, and electrolytic plating on the entire surface of the integrated circuit; (b) Forming a photoresist film with openings on the metal film (c) Using the photoresist film as a mask, perform Au plating. (d) Wet etching to remove the Au thin film and slightly remove the bump surface. (e) Ion beam etching to form a Pt thin film using the bump electrode as a mask. A method for manufacturing a semiconductor device, comprising the steps of sequentially removing a Ti thin film.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1125825A JP2874184B2 (en) | 1989-05-19 | 1989-05-19 | Method for manufacturing semiconductor device |
| KR1019890016671A KR940010510B1 (en) | 1988-11-21 | 1989-11-17 | Fabricating method of semiconductor device |
| US07/665,234 US5298459A (en) | 1988-11-21 | 1991-03-05 | Method of manufacturing semiconductor device terminal having a gold bump electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1125825A JP2874184B2 (en) | 1989-05-19 | 1989-05-19 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02304929A true JPH02304929A (en) | 1990-12-18 |
| JP2874184B2 JP2874184B2 (en) | 1999-03-24 |
Family
ID=14919874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1125825A Expired - Lifetime JP2874184B2 (en) | 1988-11-21 | 1989-05-19 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2874184B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06112213A (en) * | 1992-08-31 | 1994-04-22 | Internatl Business Mach Corp <Ibm> | Method for etching treatment |
| FR2707797A1 (en) * | 1993-07-15 | 1995-01-20 | Samsung Electronics Co Ltd | Method of manufacturing bumps for chips. |
-
1989
- 1989-05-19 JP JP1125825A patent/JP2874184B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06112213A (en) * | 1992-08-31 | 1994-04-22 | Internatl Business Mach Corp <Ibm> | Method for etching treatment |
| FR2707797A1 (en) * | 1993-07-15 | 1995-01-20 | Samsung Electronics Co Ltd | Method of manufacturing bumps for chips. |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2874184B2 (en) | 1999-03-24 |
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