JPH0444232A - Manufacture of integrated circuit - Google Patents
Manufacture of integrated circuitInfo
- Publication number
- JPH0444232A JPH0444232A JP2149221A JP14922190A JPH0444232A JP H0444232 A JPH0444232 A JP H0444232A JP 2149221 A JP2149221 A JP 2149221A JP 14922190 A JP14922190 A JP 14922190A JP H0444232 A JPH0444232 A JP H0444232A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal film
- photo resist
- forming
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 238000002161 passivation Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000007747 plating Methods 0.000 claims abstract description 5
- 239000002313 adhesive film Substances 0.000 claims abstract description 4
- 230000004888 barrier function Effects 0.000 claims abstract description 4
- 238000009713 electroplating Methods 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000008030 elimination Effects 0.000 abstract 2
- 238000003379 elimination reaction Methods 0.000 abstract 2
- 238000004806 packaging method and process Methods 0.000 abstract 2
- 239000010931 gold Substances 0.000 description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、集積回路の製造方法に関して、特に、外部接
続端子である電極用金バンプを有する集積回路に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an integrated circuit, and particularly to an integrated circuit having gold bumps for electrodes serving as external connection terminals.
従来、集積回路の電極用金バンプの製造方法に関しては
、数多くの提案がなされ、改良が加えられている。第２
図は、従来の電極用金バンプの製造工程を断面図により
示したものである。Conventionally, many proposals have been made and improvements have been made regarding methods of manufacturing gold bumps for electrodes of integrated circuits. Second
The figure is a sectional view showing the manufacturing process of a conventional gold bump for electrodes.
第２図（ａ）に示すように、集積回路表面のパッシベー
ション膜９、および電極パッド１０の上に、前記第１金
属膜（Ｔｉ膜１１）、前記第２金属膜（ｐｔ膜１２）、
前記第３金属膜（Ａｕ膜１３）を順次形成する。As shown in FIG. 2(a), the first metal film (Ti film 11), the second metal film (PT film 12),
The third metal film (Au film 13) is sequentially formed.
次に、第２図（ｂ）に示すように、前記金属膜上に、フ
ォトレジスト膜１４を塗布する。このフォトレジスト膜
１４の開口部は、パッシベーション膜開口部全体を含む
ように形成する。Next, as shown in FIG. 2(b), a photoresist film 14 is applied on the metal film. The opening of this photoresist film 14 is formed to include the entire opening of the passivation film.
次に、第２図（ｃ）に示すように、前記フォトレジスト
膜１４の開口部に電解金メッキを行い、垂直形状を有す
るバンプ型電極１５を形成する。Next, as shown in FIG. 2(c), electrolytic gold plating is applied to the opening of the photoresist film 14 to form a bump-type electrode 15 having a vertical shape.
その後、前記フォトレジスト膜１４を剥離除去する。After that, the photoresist film 14 is peeled off and removed.
次に、第２図（ｄ）に示すように、前記垂直形状を有す
るバンプ型電極１５をマスクとして、前記第１金属膜（
Ｔｉ膜１１）、前記第２金属膜（ｐｔ膜１２）、前記第
３金属膜（Ａｕ膜１３）を自己整合的に乾式エツチング
により除去する。Next, as shown in FIG. 2(d), using the bump-type electrode 15 having the vertical shape as a mask, the first metal film (
The Ti film 11), the second metal film (PT film 12), and the third metal film (Au film 13) are removed by dry etching in a self-aligned manner.
〔発明が解決しようとする課題〕
この様に形成された集積回路では、以下に示す問題があ
った。[Problems to be Solved by the Invention] The integrated circuit formed in this manner has the following problems.
従来の電極用金バンプの製造方法では、フォトレジスト
膜を塗布し、開口部を形成する工程において、フォトレ
ジスト膜の開口部がパッシベーション膜開口部全体を含
んで形成されるため、前記フォトレジスト膜をマスクと
して形成される垂直形状を有するバンプ型電極は、電極
バット上のパッシベーション膜を一部含んだ部分を下地
として形成される。この構造では、外部引出電極との接
合の際、大きな熱的・機械的ダメージを受けると、パッ
シベーション膜にクラックが入ってしまったり、電極パ
ッド下の酸化膜やシリコン基板にクラックが生じ、基板
から前記垂直形状を有するバンプ型電極が剥離してしま
う問題があった。In the conventional method for manufacturing gold bumps for electrodes, in the step of applying a photoresist film and forming an opening, the opening of the photoresist film is formed to include the entire opening of the passivation film. A bump-type electrode having a vertical shape is formed using a part of the passivation film on the electrode butt as a base. If this structure is subjected to large thermal or mechanical damage when bonding with the external lead electrode, cracks may appear in the passivation film, cracks may occur in the oxide film under the electrode pad or the silicon substrate, and the substrate may be damaged. There is a problem in that the bump-type electrode having the vertical shape peels off.
本発明は、前記従来技術の問題点を解決しようとするも
のであり、その目的は、実装時の熱的・機械的ダメージ
に強く、高い実装安定性を有する電極用金バンプを形成
する集積回路の製造方法を提供することにある。The present invention attempts to solve the problems of the prior art, and its purpose is to provide an integrated circuit for forming gold bumps for electrodes that is resistant to thermal and mechanical damage during mounting and has high mounting stability. The purpose of this invention is to provide a method for manufacturing the same.
集積回路の電極パッド上に、バンプ型電極を形成する工
程において、
集積回路全面に、密着膜としての第１金属膜を形成する
Ｉｌｌの工程と、
前記第１金属膜上に、フォトレジスト膜を形成する工程
において、電極パッド上から、パッシベーション膜開口
部の外周まで被覆するように、フォトレジスト膜を形成
する第２の工程と、前記フォトレジスト膜をマスクとし
て、前記第１金属膜をエツチングした後、前記フォトレ
ジスト膜を剥離除去する第３の工程と、
前記集積回路全面に、相互拡散バリア膜としての第２金
属膜、および、メッキ密着膜としての第３金属膜とを順
次形成する第４の工程と、前記金属膜上に、フォトレジ
スト膜を形成する工程において、その開口部がパッシベ
ーション膜開口部の内部に形成されるようにする第５の
工程と、 前記フォトレジスト膜をマスクとして、電解
メッキを行い、垂直形状を有するバンプ型電極を形成し
た後、前記フォトレジスト膜を剥離除去する第６の工程
と、
前記垂直形状を有するバンプ型電極をエツチングのマス
クとして、前記第２金属膜、第３金属膜を自己整合的に
乾式エツチング除去する第７の工程
から成ることを特徴とする集積回路の製造方法。In the step of forming bump-type electrodes on the electrode pads of the integrated circuit, a step of forming a first metal film as an adhesive film on the entire surface of the integrated circuit, and forming a photoresist film on the first metal film. In the forming step, a second step of forming a photoresist film so as to cover the electrode pad to the outer periphery of the passivation film opening, and a second step of etching the first metal film using the photoresist film as a mask. After that, a third step of peeling and removing the photoresist film, and a third step of sequentially forming a second metal film as an interdiffusion barrier film and a third metal film as a plating adhesion film on the entire surface of the integrated circuit. step 4, and a fifth step of forming a photoresist film on the metal film so that the opening is formed inside the passivation film opening, and using the photoresist film as a mask. a sixth step of performing electrolytic plating to form a bump-type electrode having a vertical shape, and then peeling off the photoresist film; and using the bump-type electrode having a vertical shape as an etching mask, the second metal is removed. A method for manufacturing an integrated circuit, comprising a seventh step of removing the film and the third metal film by dry etching in a self-aligned manner.
以下、本発明の実施例について、図面を参照して説明す
る。Embodiments of the present invention will be described below with reference to the drawings.
第１図（ａ）〜（ｇ）は、本発明の詳細な説明するため
、工程順に示した断面図である。FIGS. 1(a) to 1(g) are cross-sectional views shown in the order of steps for detailed explanation of the present invention.
第１図（ａ）に示すように、集積回路表面のパッシベー
ション膜１、および電極パッド２の上に、密着膜として
、０．２〜０．３μｍのＴｉ膜３をスパッタ法により形
成する。As shown in FIG. 1(a), a Ti film 3 of 0.2 to 0.3 μm is formed as an adhesive film on the passivation film 1 and the electrode pads 2 on the surface of the integrated circuit by sputtering.
次に、第１図（ｂ）に示すように、前記金属膜上にフォ
トレジスト膜を塗布腰電極パッド上から、パッシベーシ
ョン膜開口部の外周まで被覆するように、フォトレジス
ト膜４を形成する。Next, as shown in FIG. 1(b), a photoresist film 4 is formed by applying a photoresist film on the metal film so as to cover from the electrode pad to the outer periphery of the passivation film opening.
次に、第１図（ｃ）に示すように、前記フォトレジスト
膜４をマスクとして、前記Ｔｉ膜３をエツチング除去し
、その後、前記フォトレジスト膜４を剥離除去する。Next, as shown in FIG. 1(c), the Ti film 3 is etched away using the photoresist film 4 as a mask, and then the photoresist film 4 is peeled off.
次に、第１図（ｄ）に示すように、前記集積回路全面に
、相互拡散バリア膜として、０．１〜０゜２μｍのｐｔ
膜５、および、メッキ密着膜として、０．１〜０．２μ
ｍのＡｕ膜６を順次、スパッタ法により形成する。Next, as shown in FIG. 1(d), a PT of 0.1 to 0.2 μm is coated over the entire surface of the integrated circuit as a mutual diffusion barrier film.
As the film 5 and the plating adhesion film, 0.1 to 0.2μ
m Au films 6 are sequentially formed by sputtering.
次に、第１図（ｅ）に示すように、前記金属膜上に、フ
ォトレジスト膜７を塗布し、その開口部をパッシベーシ
ョン膜開口部の内部に形成する。Next, as shown in FIG. 1(e), a photoresist film 7 is applied on the metal film, and its opening is formed inside the passivation film opening.
次に、第１図（ｆ）に示すように、前記フォトレジスト
膜７をマスクとして、電解メッキを行い、垂直形状を有
するバンプ型電極８を形成し、その後、前記フォトレジ
スト膜７を剥離除去する。Next, as shown in FIG. 1(f), electrolytic plating is performed using the photoresist film 7 as a mask to form a bump-type electrode 8 having a vertical shape, and then the photoresist film 7 is peeled off. do.
次に、第１図（ｇ）に示すように、イオンミリング等の
乾式エツチングにより、前記垂直形状を有するバンプ型
電極８をマスクとして、前記ｐｔ膜５、Ａｕ膜を自己整
合的にエツチング除去する。Next, as shown in FIG. 1(g), the PT film 5 and the Au film are removed by dry etching such as ion milling in a self-aligned manner using the vertically shaped bump electrode 8 as a mask. .
以上の工程により、パッシベーション膜を含むことなく
、電極パッドのみを下地として、垂直形状を有するバン
プ型電極が、集積回路上に形成される。Through the above steps, a bump-type electrode having a vertical shape is formed on the integrated circuit using only the electrode pad as a base without including a passivation film.
このようにして形成された垂直形状を有するバンプ型電
極は、実装時の熱的・機械的ダメージが電極パッドで吸
収される構造になっているため、高い実装安定性を有す
る。The bump-type electrode having a vertical shape formed in this manner has a structure in which thermal and mechanical damage during mounting is absorbed by the electrode pad, and therefore has high mounting stability.
また、電極パッドからパッシベーション膜開口部の外周
まで、Ｔｉ膜によって被覆されているため、電極パッド
の露出がない。従って、ＡＬの腐食等の信頼性上の問題
もない。Further, since the electrode pads are covered with the Ti film from the electrode pads to the outer periphery of the passivation film opening, the electrode pads are not exposed. Therefore, there are no reliability problems such as AL corrosion.
以上説明したように、本発明によれば、実装時の熱的・
機械的ダメージに強く、高い実装安定性を確保できる、
垂直形状を有するバンプ型電極が形成可能となる。As explained above, according to the present invention, the thermal
Resistant to mechanical damage and can ensure high mounting stability.
A bump-type electrode having a vertical shape can be formed.
第１図＜ａ＞〜（ｇ）は、本発明の詳細な説明するため
の工程順に示した断面図である。
第２図（ａ）〜（ｄ）は、従来技術を説明するための工
程順に示した断面図である。
１ ・
２ ・
３ ・
４ ・
５ ・
６ ・
７ ・
８・
９ ・
１０ ・
１１ ・
１２ ・
１３ ・
パッシベーション膜
電極パッド
Ｔｉ膜
フォトレジスト膜
ｐｔ膜
Ａｕ膜
フォトレジスト膜
垂直形状を有するバンプ型電極
パッシベーション膜
電極パッド
Ｔｉ膜
Ｐｔ膜
Ａｕ膜
１４・・・フォトレジスト膜
１５・・・垂直形状を有するバンプ型電極以上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴 木 喜三部（他１名）肇２図
す
潴２ＩＺｌFIGS. 1<a> to 1(g) are cross-sectional views shown in the order of steps for detailed explanation of the present invention. FIGS. 2(a) to 2(d) are cross-sectional views shown in the order of steps for explaining the prior art. 1 ・ 2 ・ 3 ・ 4 ・ 5 ・ 6 ・ 7 ・ 8 ・ 9 ・ 10 ・ 11 ・ 12 ・ 13 ・ Passivation film Electrode pad Ti film Photoresist film PT film Au film Photoresist film Bump type electrode passivation with vertical shape Membrane electrode pad Ti film Pt film Au film 14... Photoresist film 15... Vertical bump type electrode or above Applicant Seiko Epson Corporation Agent Patent attorney Kizobe Suzuki (1 other person) Hajime 2 Figure 2 IZl
Claims (1)
方法において、集積回路全面に、密着膜としての第１金
属膜を形成する第１の工程と、前記第１金属膜上に、フ
ォトレジスト膜を形成する工程において、電極パッド上
から、パッシベーション開口部の外周まで被覆するよう
に、フォトレジスト膜を形成する第２の工程と、 前記フォトレジスト膜をマスクとして、前記第１金属膜
をエッチングした後、前記フォトレジスト膜を剥離除去
する第３の工程と、前記集積回路全面に、相互拡散バリ
ア膜としての第２金属膜、および、メッキ密着膜として
の第３金属膜とを順次形成する第４の工程と、前記金属
膜上に、フォトレジスト膜を形成する工程において、そ
の開口部がパッシベーション開口部の内部に形成される
ようにする第５の工程と、前記フォトレジスト膜をマス
クとして、電解メッキを行い、垂直形状を有するバンプ
型電極を形成した後、前記フォトレジスト膜を剥離除去
する第６の工程と、 前記垂直形状を有するバンプ型電極をエッチングのマス
クとして、前記第２金属膜、第３金属膜を自己整合的に
乾式エッチング除去する第７の工程から成ることを特徴
とする、集積回路の製造方法。[Claims] A method for forming a bump-type electrode on an electrode pad of an integrated circuit, comprising: a first step of forming a first metal film as an adhesive film over the entire surface of the integrated circuit; and the first metal film. a second step of forming a photoresist film so as to cover from the top of the electrode pad to the outer periphery of the passivation opening; After etching the first metal film, a third step of peeling off the photoresist film, and applying a second metal film as a mutual diffusion barrier film and a third metal film as a plating adhesion film to the entire surface of the integrated circuit. a fourth step of sequentially forming a photoresist film on the metal film, a fifth step of forming a photoresist film so that the opening is formed inside the passivation opening; A sixth step of performing electrolytic plating using the resist film as a mask to form a bump-type electrode having a vertical shape, and then peeling and removing the photoresist film, and using the bump-type electrode having the vertical shape as a mask for etching. . A method for manufacturing an integrated circuit, comprising a seventh step of removing the second metal film and the third metal film by dry etching in a self-aligned manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149221A JPH0444232A (en) | 1990-06-07 | 1990-06-07 | Manufacture of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149221A JPH0444232A (en) | 1990-06-07 | 1990-06-07 | Manufacture of integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0444232A true JPH0444232A (en) | 1992-02-14 |
Family
ID=15470506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2149221A Pending JPH0444232A (en) | 1990-06-07 | 1990-06-07 | Manufacture of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0444232A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100450243B1 (en) * | 2002-04-09 | 2004-09-24 | 아남반도체 주식회사 | A manufacturing method of bump for semiconductor device |
-
1990
- 1990-06-07 JP JP2149221A patent/JPH0444232A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100450243B1 (en) * | 2002-04-09 | 2004-09-24 | 아남반도체 주식회사 | A manufacturing method of bump for semiconductor device |
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