JPH02139933A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02139933A JPH02139933A JP63293999A JP29399988A JPH02139933A JP H02139933 A JPH02139933 A JP H02139933A JP 63293999 A JP63293999 A JP 63293999A JP 29399988 A JP29399988 A JP 29399988A JP H02139933 A JPH02139933 A JP H02139933A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- sputtering
- tin
- diffusion barrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000010931 gold Substances 0.000 claims abstract description 27
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052737 gold Inorganic materials 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 238000009713 electroplating Methods 0.000 claims abstract description 4
- 238000007747 plating Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 6
- 238000002161 passivation Methods 0.000 abstract description 5
- 239000011241 protective layer Substances 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 238000000992 sputter etching Methods 0.000 abstract description 2
- 235000010210 aluminium Nutrition 0.000 abstract 2
- 239000000470 constituent Substances 0.000 abstract 1
- 230000007797 corrosion Effects 0.000 abstract 1
- 238000005260 corrosion Methods 0.000 abstract 1
- 238000005546 reactive sputtering Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000001580 bacterial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
〔産業上の利用分野〕
本発明は半導体装置の構造に関し、特に外部端子である
電極用金バンブを有する半導体装置に関する。
〔従来の技術Ｊ
従来、半導体装置の電極用金バンブの構造に関しては数
多くの提案がなされ、改良が加えられている。第２図は
、集積回路上に形成された電極用金バンブの断面図であ
る。
第２図に示すように集積回路上の金バンブは。
密着層であるＣｒ膿２５．拡散バリア層であるＣｕ膜２
６．保護層であるＡｕ膿２７を付着させた後、その上に
金メッキ部２８を形成するような構造をとっていた。こ
のような材料にて形成された金バンブは、Ｃｒ膜２５、
Ｃｕ嗅２６が大気に晒されているために、高湿度の雰囲
気で使用した場合、Ｃｒ膜２５、Ｃｕ膿２６が腐食する
という欠点があった。
〔発明が解決しようとする課題〕
本発明の目的は、上記欠点を解決しようとするもので、
高湿度雰囲気で使用しても腐食しないＴｉ膜及びＴｉＮ
１ｌを用い、高信頼性半導体装置を提供することにある
。[Industrial Field of Application] The present invention relates to the structure of a semiconductor device, and particularly to a semiconductor device having gold bumps for electrodes serving as external terminals. [Prior Art J] Conventionally, many proposals have been made and improvements have been made regarding the structure of gold bumps for electrodes of semiconductor devices. FIG. 2 is a cross-sectional view of a gold bump for an electrode formed on an integrated circuit. The gold bumps on the integrated circuit are shown in Figure 2. Adhesive layer Cr pus25. Cu film 2 as a diffusion barrier layer
6. The structure was such that after adhering Au pus 27 as a protective layer, a gold plated portion 28 was formed thereon. A gold bump formed of such a material has a Cr film 25,
Since the Cu film 26 is exposed to the atmosphere, there is a drawback that the Cr film 25 and the Cu film 26 corrode when used in a high humidity atmosphere. [Problem to be solved by the invention] The purpose of the present invention is to solve the above-mentioned drawbacks.
Ti film and TiN that do not corrode even when used in high humidity atmosphere
The object of the present invention is to provide a highly reliable semiconductor device using 1L.
拡散、絶縁膜、配線を形成した集積回路の前記絶縁膜及
び配線の上に、密着層としてのＴｉ膜、拡散バリア層と
してのＴｉＮ膜、メッキＦ地層であるＡｕ膜、及び電解
メッキによる金バンブにより構成される電極が形成され
て成ることを特徴とする半導体装置。A Ti film as an adhesion layer, a TiN film as a diffusion barrier layer, an Au film as a plating F layer, and a gold bump formed by electrolytic plating are placed on the insulating film and wiring of the integrated circuit in which the diffusion, insulating film, and wiring have been formed. 1. A semiconductor device comprising an electrode formed of:
【実 施 例１
以下に、本発明について、製造方法の実施例にもとづき
詳細に説明をする。
第１図にあるように、本発明の電極用金バンプは、シリ
コン基板膜、シリコン酸化膜１２、アルミ電極パッド１
３及びパッシベーション膜１４から成る集積回路上に形
成する。
アルミ電極パッド１３及びパッシベーション膜１４との
密着を得るためのＴｉ膜１５をスパッタリング法にてＯ
，ｌｕｍ、拡散バリアとしてのＴｉＮ１ｉ１６を反応性
スパックリング法にて０．１ｇｍ、保護層としてのＡｕ
１ｌｌ１７をスパッタリング法にてＯ，ｌｕｍ形成する
。
次に、２０μｍ以上の膜厚のフォトレジストパターンを
用いて、メッキ部１８を電解メッキ法により２０ｕｍ厚
になるように形成する。
次に、メッキ部１８をマスクとして、Ａｕ膜１７、Ｔｉ
Ｎｌ１ｉ１６、Ｔ ｉ ｌ！ １５をイオンミーリング
法を用いてエツチングすると１図１のような電極用金バ
ンブを得ることができる。
【発明の効果】
本発明は、半導体装置の電棲用金バンブにおいて、密着
層としてＴ ｉ １！、拡散バリア層としてＴｉＮ膜、
保護層としてＡｕ！ｉを用いることにより、高湿度雰囲
気で使用しても菌膜が腐食せず。
高い信頼性の金バンブを得ることができた。さらに、使
用電圧も従来より高く、より有用で使用性の高い金バン
ブを得ることができた。[Example 1] The present invention will be described in detail below based on an example of a manufacturing method. As shown in FIG. 1, the gold bump for electrode of the present invention includes a silicon substrate film, a silicon oxide film 12, an aluminum electrode pad 1
3 and a passivation film 14. The Ti film 15 is coated with O2 by sputtering to obtain close contact with the aluminum electrode pad 13 and the passivation film 14.
, lum, 0.1 gm of TiN1i16 as a diffusion barrier by reactive spackling method, and Au as a protective layer.
1ll17 is formed to a thickness of O, lum by a sputtering method. Next, using a photoresist pattern with a thickness of 20 μm or more, the plated portion 18 is formed to have a thickness of 20 μm by electrolytic plating. Next, using the plated portion 18 as a mask, the Au film 17 and the Ti
Nl1i16, T i l! By etching 15 using an ion milling method, a gold bump for an electrode as shown in FIG. 1 can be obtained. Effects of the Invention The present invention provides a gold bump for electrolyzing a semiconductor device in which T i 1! is used as an adhesion layer. , a TiN film as a diffusion barrier layer,
Au as a protective layer! By using i, the bacterial film does not corrode even when used in a high humidity atmosphere. We were able to obtain highly reliable gold bumps. Furthermore, the working voltage was higher than before, making it possible to obtain gold bumps that were more useful and had higher usability.
第１図は、本発明の実施例によるバンブ型電極の断面図
。
第２図は、従来のバンブ型電極の断面図。
１１・・・シリコン基板
１２・・・シリコン酸化膜
ｌ ３ ・
ｌ ４ ・
ｌ ５ ・
１６ ・
ｌ ７ ・
ｌ ８ ・
２１ ・
２２ ・
２３ ・
２４ ・
２５ ・
２６ ・
２７ ・
２８ ・
アルミ電極パッド
パッシベーション膜
Ｔｉ１ｌ！
ＴｉＮ膜
Ａｕｔｌ！
Ａｕメッキ部
シリコン基板
シリコン酸化膜
アルミ電極パッド
パッシベーション膜
ＣｒＨ￥ｉ
Ｃｕ膜
Ａｕ膜
Ａｕメッキ部
１１図
以
上
出願人 セイコーエプソン株式会社
代理人 弁理士 上 柳 雅 誉−（他１名）算２図FIG. 1 is a sectional view of a bump-type electrode according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a conventional bump-type electrode. 11...Silicon substrate 12...Silicon oxide film l3, l4, l5, 16, l7, l8, 21, 22, 23, 24, 25, 26, 27, 28, aluminum electrode pad passivation Membrane Ti1l! TiN film Autl! Au plating part Silicon substrate Silicon oxide film Aluminum electrode pad Passivation film CrH￥i Cu film Au film Au plating part 11 figures or more Applicant Seiko Epson Corporation Representative Patent attorney Homare Kamiyanagi (1 other person) Calculation 2 figures
Claims (1)
び配線の上に、密着層としてのＴｉ膜、拡散バリア層と
してのＴｉＮ膜、メッキ下地層であるＡｕ膜、及び電解
メッキによる金バンプにより構成される電極が形成され
て成ることを特徴とする半導体装置。A Ti film as an adhesion layer, a TiN film as a diffusion barrier layer, an Au film as a plating base layer, and gold bumps by electrolytic plating are placed on the insulating film and wiring of the integrated circuit in which the diffusion, insulating film, and wiring have been formed. 1. A semiconductor device comprising an electrode formed of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63293999A JPH02139933A (en) | 1988-11-21 | 1988-11-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63293999A JPH02139933A (en) | 1988-11-21 | 1988-11-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02139933A true JPH02139933A (en) | 1990-05-29 |
Family
ID=17801934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63293999A Pending JPH02139933A (en) | 1988-11-21 | 1988-11-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02139933A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5550427A (en) * | 1991-11-19 | 1996-08-27 | Nec Corporation | Substrate contact electrode having refractory metal bump structure with reinforcement sidewall film |
| US5663598A (en) * | 1993-12-13 | 1997-09-02 | Micron Communications, Inc. | Electrical circuit bonding interconnect component and flip chip interconnect bond |
| US6157079A (en) * | 1997-11-10 | 2000-12-05 | Citizen Watch Co., Ltd | Semiconductor device with a bump including a bump electrode film covering a projecting photoresist |
| WO2005057629A3 (en) * | 2003-12-09 | 2005-09-29 | Infineon Technologies Ag | Assembly and adhesive layer for semiconductor components |
| JP2015162583A (en) * | 2014-02-27 | 2015-09-07 | シーメンス アクチエンゲゼルシヤフトＳｉｅｍｅｎｓ Ａｋｔｉｅｎｇｅｓｅｌｌｓｃｈａｆｔ | Electrode provided with ubm structure and method for producing the same |
-
1988
- 1988-11-21 JP JP63293999A patent/JPH02139933A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5550427A (en) * | 1991-11-19 | 1996-08-27 | Nec Corporation | Substrate contact electrode having refractory metal bump structure with reinforcement sidewall film |
| US5663598A (en) * | 1993-12-13 | 1997-09-02 | Micron Communications, Inc. | Electrical circuit bonding interconnect component and flip chip interconnect bond |
| US5804876A (en) * | 1993-12-13 | 1998-09-08 | Micron Communications Inc. | Electronic circuit bonding interconnect component and flip chip interconnect bond |
| US6114239A (en) * | 1993-12-13 | 2000-09-05 | Micron Communications, Inc. | Electronic circuit bonding interconnect component and flip chip interconnect bond |
| US6157079A (en) * | 1997-11-10 | 2000-12-05 | Citizen Watch Co., Ltd | Semiconductor device with a bump including a bump electrode film covering a projecting photoresist |
| WO2005057629A3 (en) * | 2003-12-09 | 2005-09-29 | Infineon Technologies Ag | Assembly and adhesive layer for semiconductor components |
| JP2015162583A (en) * | 2014-02-27 | 2015-09-07 | シーメンス アクチエンゲゼルシヤフトＳｉｅｍｅｎｓ Ａｋｔｉｅｎｇｅｓｅｌｌｓｃｈａｆｔ | Electrode provided with ubm structure and method for producing the same |
| US10347774B2 (en) | 2014-02-27 | 2019-07-09 | Siemens Aktiengesellschaft | Electrode provided with UBM structure having a barrier layer for reducing solder diffusion into the electrode and a method for producing the same |
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