JPS58192351A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS58192351A
JPS58192351A JP57076089A JP7608982A JPS58192351A JP S58192351 A JPS58192351 A JP S58192351A JP 57076089 A JP57076089 A JP 57076089A JP 7608982 A JP7608982 A JP 7608982A JP S58192351 A JPS58192351 A JP S58192351A
Authority
JP
Japan
Prior art keywords
film
barrier metal
thin
metal layer
noble metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57076089A
Other languages
Japanese (ja)
Inventor
Yasunori Senkawa
保憲 千川
Katsunobu Mori
勝信 森
Takamichi Maeda
前田 崇道
Masao Hayakawa
早川 征男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP57076089A priority Critical patent/JPS58192351A/en
Publication of JPS58192351A publication Critical patent/JPS58192351A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the damage of Al wiring, and to improve the reliability and yield of the device by etching a barrier metal as a foundation under the state in which a noble metal thin-film of specific thickness or less is left on a barrier metal layer. CONSTITUTION:An Al electrode pad 2 on a semiconductor substrate 1 is coated with a protective film 3, and a Ti layer 4 and an Au film 9 of not more than 1,000Angstrom thickness are evaporated onto the film 3 and the pad 2. A resist mask 6 is executed, the surface is plated with Au, and a bump electrode 8 is formed. When the mask 6 is removed and the surface of the substrate is exposed in an H2O2 group liquid, an etching liquid intrudes through defects such as the pin holes of the thin-film 9, and etches the foundation barrier metal 4, but Al is hardly etched. Accordingly, the Au thin-film 9 floats from the surface of the substrate in sections except a pad section. The thin-film 9 under an unstable state is removed easily through ultrasonic washing under the state. According to the constitution, an unnecessary Au thin-film is removed easily, Al wiring is not damaged by the severe etching liquid, and the reliability and yield of the device can be improved.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関し、特にチップの電
極パッド上に突起電極を@え−た半導体装置に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device in which protruding electrodes are provided on electrode pads of a chip.

半導体チップに組込まれた回路素子を外部回路と接続す
るために通常チップ周囲の表面に電極・くラドを作製し
、更に該電極パッド上に突起電極(バンプ)を作製して
インナリードの先端や、ビームリードの先端等を接続す
ることにより、外部接続用リード線を備えた半導体装置
を作製している。この種の突起電極としてAuバンプ、
半田バンブが広く利用されており、次にまず従来から用
いられているAuバンプの作製工程について説明する。
In order to connect circuit elements built into a semiconductor chip with external circuits, electrodes and pads are usually fabricated on the surface around the chip, and protruding electrodes (bumps) are fabricated on the electrode pads to connect the tips of inner leads and By connecting the tips of beam leads, etc., a semiconductor device equipped with lead wires for external connection is manufactured. Au bumps are used as this kind of protruding electrodes.
Solder bumps are widely used, and the manufacturing process of conventionally used Au bumps will be described first.

第1図(a)において、lは半導体基板で従来公知の半
導体製造技術によってトランジスタ、抵抗等の回路素子
が組込まれている。該基板表面には、回路素子間のAI
!配線と一体的にチップ周辺領域を利用してAI!電極
バッド2が形成されると共に、バッド20部分ヲ除いて
パッシベーション膜3で基板表面が被われている。パッ
シベーション膜3で被われた基板1上には、Ti又はT
i合金からなる下地バリア金属層4、続いて貴金属から
なるg出層パす7金属層5f′”順次蒸着によ°て積層
されている。上記2層からなるバリア金属層上には第1
図(鶴に示す如く次にフォトレジスト6が塗布され、フ
ォトリングラフィ工程を経て電極パッド2に相当する位
置に窓開ロアが形成される。窓開ロアを介して電気メッ
キによシバリア金属層上にAuバンプ8が形成され、レ
ジスト6が除去されると共に、形成されたAuバンプ8
をマスクに上層バリア金属層5及び下地バリア金属層4
が順次エツチング除去されて、第1図(c)に示す如く
突起電極8を備えた半導体装置を作製している。
In FIG. 1(a), reference numeral 1 denotes a semiconductor substrate into which circuit elements such as transistors and resistors are incorporated using conventionally known semiconductor manufacturing techniques. On the surface of the substrate, there is an AI between circuit elements.
! AI using the chip peripheral area in conjunction with wiring! The electrode pad 2 is formed, and the surface of the substrate is covered with a passivation film 3 except for the pad 20 portion. On the substrate 1 covered with the passivation film 3, Ti or T
A base barrier metal layer 4 made of an i-alloy, followed by a g-layer pass 7 metal layer 5f' made of a noble metal are deposited by sequential vapor deposition.
As shown in the figure (crane), a photoresist 6 is then applied, and a window opening lower is formed at a position corresponding to the electrode pad 2 through a photolithography process. Au bumps 8 are formed thereon, the resist 6 is removed, and the formed Au bumps 8 are removed.
Upper barrier metal layer 5 and base barrier metal layer 4 using as a mask
are sequentially removed by etching to produce a semiconductor device equipped with protruding electrodes 8 as shown in FIG. 1(c).

ここで上記2層バリア金属層4及び5は、Auバンブ8
とAI!電極パ・1ド2との相互拡散を防き、またAt
電極パッド2との密着性、メッキによるAuバンブ8と
の密着性向上のために設けられている。このような目的
に合ったバリア金属材料の組合せとしてPt、Au、P
d等の貴金属とTiやTi合金の2層ないし3層の組合
せが一例として挙げられる。
Here, the two-layer barrier metal layers 4 and 5 are composed of Au bumps 8
And AI! It prevents mutual diffusion with electrode pads 1 and 2, and also prevents At
It is provided to improve the adhesion with the electrode pad 2 and the adhesion with the Au bump 8 by plating. Pt, Au, and Pt are combinations of barrier metal materials suitable for this purpose.
An example is a combination of two or three layers of a noble metal such as d and Ti or a Ti alloy.

特に突起電極としてAuが用いられる場合には”、(:
’、、’4 uメ・キとの密着性、メ・キ性の向上から
上層Lン5゛ バリア金属の貴金属はバリアメタル層を構成する上で必
要不可欠の層である。しかし一般に用いられてbるPt
、AujPd等の貴金属は、耐酸性、耐アルカリ性にす
ぐれているため、このような性質は反面で半導体装置の
製造工程に障害となる。即ち半導体基板の表面を被って
蒸着された下地バリア金属及び貴金属は、突起電極のだ
めのバリア金属領域となる部分以外の不必要な部分は除
去されねばならない。しかし貴金属は上述のような性質
のために化学的にエツチング除去することが非常に困難
で、他の素材に対してもエツチング作用の強い王水やヨ
ウ素系のエッチャントを用いる方法や、プラズマ等のド
ライエツチングによる方法が採用されている。
Especially when Au is used as the protruding electrode,
',,'4 The noble metal of the upper layer L-5 barrier metal is an indispensable layer in forming the barrier metal layer because it improves the adhesion with the metal layer and the metallization property. However, commonly used Pt
, AujPd, and the like have excellent acid resistance and alkali resistance, and on the other hand, such properties become an obstacle in the manufacturing process of semiconductor devices. That is, unnecessary portions of the base barrier metal and noble metal deposited over the surface of the semiconductor substrate must be removed, except for the portions that will become barrier metal regions for the protruding electrodes. However, due to the above-mentioned properties, it is extremely difficult to chemically remove precious metals by etching them. A dry etching method is used.

しかし前者の化学エツチングでは貴金属を完全に除去し
ない内に、ステップ部の膜厚の薄い部分や膜のピンホー
ル部、バンブ部界面等を通してエッチャントが浸入し、
最下層に設けられたAl電極パッド2や配線が浸食され
て断線や接触不良を謳 一′ しる原因になる。
However, in the former type of chemical etching, the etchant penetrates through the thin part of the step part, the pinhole part of the film, the interface of the bump part, etc. before the precious metal is completely removed.
The Al electrode pads 2 and wiring provided on the lowest layer are eroded, causing disconnection and poor contact.

長くなり、作業効率が著しく悪いという欠点があった。The problem was that it was long and the work efficiency was extremely low.

本発明は上記従来の半導体装rltKおける突起電極の
作製工程における問題点に鑑みてなされたもので、次に
実施例を挙げて本発明を説明する。
The present invention has been made in view of the problems in the process of manufacturing protruding electrodes in the conventional semiconductor device rltK, and the present invention will now be described with reference to Examples.

本発明を要約すれば、バリア金属層の上部を比較的薄い
膜厚の貴金属層で構成し、突起電極となる導体を作製し
た後貴金属層を残した状態でF層の下地バリア金属をエ
ツチングし、その後基板表面から浮いた不要な貴金属部
分を除去するものである。
To summarize the present invention, the upper part of the barrier metal layer is composed of a comparatively thin noble metal layer, and after the conductor serving as the protruding electrode is fabricated, the underlying barrier metal of the F layer is etched with the noble metal layer remaining. , and then remove unnecessary noble metal parts floating from the substrate surface.

第2図(a)において、半導体基板lの表面には、上述
の従来工程と同様にAI!電極バッド2が形成されると
共に、パッシベーション膜3で被われ、該パッジベージ
ジン膜3及び電極パッド2上にバリア金属のためのTi
又はTi合金からなる下地金属層4及びAu s P 
を又はPdからなる貴金属層9が形成されている。ここ
で特に貴金属層9は膜厚がxoooX以下、好ましくは
700Å以下の薄い膜厚に形成されている。該薄膜の形
成は、蒸着時に1oooA以下になるように時間等を制
御したり、或りは予め比較的厚く蒸着された貴金属膜を
プラズマ等のドライエツチング着しくけ王水系のエッチ
ャントによる化学エッチで1000Å以下にすることに
よって得られる。
In FIG. 2(a), the surface of the semiconductor substrate l is coated with AI! as in the conventional process described above. The electrode pad 2 is formed and covered with a passivation film 3, and Ti for barrier metal is formed on the passivation film 3 and the electrode pad 2.
Or base metal layer 4 made of Ti alloy and Au s P
A noble metal layer 9 made of Pd or Pd is formed. In particular, the noble metal layer 9 is formed to have a thickness of xoooX or less, preferably 700 Å or less. The thin film can be formed by controlling the time during vapor deposition so that the thickness is less than 100A, or by dry etching a relatively thick noble metal film with plasma or by chemically etching it with an aqua regia-based etchant. This can be obtained by reducing the thickness to 1000 Å or less.

上記薄い貴金属膜9で被われた基板表面は、第2図(b
)のようにフォトレジスト6が塗布され、フォトリング
ラフィによってバターニングされた後、突起電極8のた
めのAuメッキが施こされ、貴金属層9に連続した電極
が形成される。次に不要になったレジスト6が除去され
て第2図(clに示す基板表面を得る。続いて基板表面
を被っている貴金属層9を残した状態で、Ti又はTi
合金のエッチャントであるHlo、系の溶液に基板表面
が晒される。貴金属層゛9は上述のように予め薄く形成
されているため、ピンホールやステップ部等の欠陥が多
く含まれておシ、これらの部分を通してエッチャントが
侵入し、下地バリア金属4のエッチングが行われる。下
地バリア金属4を除去するための上記エツチング液は、
A7 K対するエツチング速度が極めて遅く、バリア金
属のエツチング処理中にAI!が侵食されることはほと
んどない。
The substrate surface covered with the thin noble metal film 9 is shown in FIG.
) After a photoresist 6 is applied and patterned by photolithography, Au plating for the protruding electrodes 8 is performed, and electrodes continuous to the noble metal layer 9 are formed. Next, the unnecessary resist 6 is removed to obtain the substrate surface shown in FIG.
The substrate surface is exposed to a solution of Hlo, an alloy etchant. Since the noble metal layer 9 is formed thin in advance as described above, it contains many defects such as pinholes and step parts, and the etchant penetrates through these parts and etches the underlying barrier metal 4. be exposed. The etching solution for removing the underlying barrier metal 4 is as follows:
The etching speed for A7 K is extremely slow, and AI! is rarely eroded.

下地バリア金属層4のエツチングが進む結果、基板表面
は第2図(d)に示す如く貴金属層9が、電極バッド部
での接合を除いて基板表面から浮いた状態になる。この
ような状態で次に基板1は溶剤中で超音波洗浄される。
As a result of the progress of etching of the underlying barrier metal layer 4, the noble metal layer 9 becomes floating from the substrate surface except for the bonding at the electrode pad portion, as shown in FIG. 2(d). In this state, the substrate 1 is then subjected to ultrasonic cleaning in a solvent.

該超音波洗浄工程中に、不安定な状態にある下地バリア
金属が除去された貴金属層部分は物理的に引きはがされ
、第2図telに示すように不要々バリア金属部分が除
去された半導体装置を得る。通常電極バッド部分では蒸
着されたバリア金属層にステップが生じてbるため、上
記超音波を作用させることによ−・て容易に除去するこ
とができる。
During the ultrasonic cleaning process, the noble metal layer portion from which the underlying barrier metal was removed was physically peeled off, and as shown in Figure 2, unnecessary barrier metal portions were removed. Obtain a semiconductor device. Usually, a step is formed in the deposited barrier metal layer at the electrode pad portion, so that it can be easily removed by applying the ultrasonic waves.

上記超音波による貴金属層9の除去は、従来のエツチン
グに比べてAl電極や配線を損う惧れがなく、また既に
作製された。Au突起電極をエツチングする量も少なく
て済み、他に与える影響を著しく小さくすることができ
る。また上記洗浄工程は、前工程までに付着した水分が
アルコールに置換されるため、洗浄の効果をも果す。
Removal of the noble metal layer 9 using ultrasonic waves has no risk of damaging the Al electrodes and wiring, compared to conventional etching, and is also possible since they have already been produced. The amount of Au protruding electrodes to be etched is also small, and the influence on other parts can be significantly reduced. In addition, the above-mentioned cleaning process also has a cleaning effect because the water that has adhered up to the previous process is replaced with alcohol.

尚、本発明によるバリア金属層は、貴金属層の1漢厚が
従′来の工程を経て作製されたものに比べて薄くなるが
、At電極バッドとAu突起電極部分とを接合させる作
用に何等支障は々い。
Although the barrier metal layer according to the present invention is thinner than that of the noble metal layer produced through the conventional process, it has no effect on the effect of bonding the At electrode pad and the Au protruding electrode portion. There are many obstacles.

以上本発明によれば、バリア層を介して突起電極を形成
した半導体装置において、バリア金属層の上部貴金属層
を比較的薄い1漢厚で形成して、貴金属層を残した状態
で下地バリア金属をエツチングすることにより、不要貴
金属層の除去が容易になり、厳し−エッチング液等によ
ってAl配線を損うこともなく半導体装置の信頼性、歩
留を著しく改善することができる。また製造工程中に危
険性の高いエツチング液を使う必要かなく、処理がし易
くなる。
As described above, according to the present invention, in a semiconductor device in which a protruding electrode is formed through a barrier layer, the upper noble metal layer of the barrier metal layer is formed to have a relatively thin thickness of 1 cm, and the underlying barrier metal layer is formed with the noble metal layer remaining. By etching, the unnecessary precious metal layer can be easily removed, and the reliability and yield of semiconductor devices can be significantly improved without damaging the Al wiring by harsh etching solutions or the like. Furthermore, there is no need to use a highly dangerous etching solution during the manufacturing process, making processing easier.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(c)は従来の製造工程を示す断面図、
第2図(a)〜(e)は本発明による実施例を示す断面
図である。 l:半導体基板、  2:At電極バッド、4:下地バ
リアメタル、 9:賞金MW、8:突起電極。 代理人 弁理士 福 士 愛 彦(他2名)1\ 1            ) N−偽 \。 258−
FIGS. 1(a) to (c) are cross-sectional views showing conventional manufacturing processes;
FIGS. 2(a) to 2(e) are cross-sectional views showing embodiments of the present invention. 1: Semiconductor substrate, 2: At electrode pad, 4: Base barrier metal, 9: Prize MW, 8: Projection electrode. Agent Patent Attorney Aihiko Fukushi (2 others) 1\1) N-False\. 258-

Claims (1)

【特許請求の範囲】[Claims] L チップ上の電極パッドに上層が貴金属からなる多層
のバリアメタル層を介して突起電極を形成してなる半導
体装置の製造方法において、下地バリア金属層上に10
00λ以下の薄い膜厚からなる貴金属膜をデポジットす
る工程と、該貴金属膜上に突起電極のための導体をデポ
ジットする工程と、該導体をマスクにして上層貴金属を
残して下地バリア金属層をエツチング除去する工程と、
下地バリア金属層から浮いて残存する上層貴金属を物理
的に除去する工程とを備えてなることを特徴とする半導
体装置の製造方法。
L. In a method for manufacturing a semiconductor device in which a protruding electrode is formed on an electrode pad on a chip through a multilayer barrier metal layer whose upper layer is a noble metal, a protruding electrode is formed on an underlying barrier metal layer.
A process of depositing a noble metal film with a thin film thickness of 00λ or less, a process of depositing a conductor for a protruding electrode on the noble metal film, and etching the base barrier metal layer using the conductor as a mask and leaving the upper noble metal layer. a step of removing;
1. A method for manufacturing a semiconductor device, comprising the step of physically removing an upper noble metal floating and remaining from a base barrier metal layer.
JP57076089A 1982-05-06 1982-05-06 Manufacture of semiconductor device Pending JPS58192351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57076089A JPS58192351A (en) 1982-05-06 1982-05-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57076089A JPS58192351A (en) 1982-05-06 1982-05-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58192351A true JPS58192351A (en) 1983-11-09

Family

ID=13595102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57076089A Pending JPS58192351A (en) 1982-05-06 1982-05-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58192351A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5310699A (en) * 1984-08-28 1994-05-10 Sharp Kabushiki Kaisha Method of manufacturing a bump electrode
US7732935B2 (en) 2004-08-12 2010-06-08 Ricoh Company, Ltd. Wiring board, electronic circuit board, electronic apparatus and manufacturing method of electronic circuit board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5310699A (en) * 1984-08-28 1994-05-10 Sharp Kabushiki Kaisha Method of manufacturing a bump electrode
US7732935B2 (en) 2004-08-12 2010-06-08 Ricoh Company, Ltd. Wiring board, electronic circuit board, electronic apparatus and manufacturing method of electronic circuit board

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