JPS5815254A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPS5815254A
JPS5815254A JP56114140A JP11414081A JPS5815254A JP S5815254 A JPS5815254 A JP S5815254A JP 56114140 A JP56114140 A JP 56114140A JP 11414081 A JP11414081 A JP 11414081A JP S5815254 A JPS5815254 A JP S5815254A
Authority
JP
Japan
Prior art keywords
layer
metal layer
solder bump
bump electrode
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56114140A
Other languages
Japanese (ja)
Inventor
Haruo Shimamoto
晴夫 島本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56114140A priority Critical patent/JPS5815254A/en
Publication of JPS5815254A publication Critical patent/JPS5815254A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To reduce the number of dipping a solder bump electrode in an etchant by forming a metal layer having good bonding strength with a wiring metal layer in the prescribed shape before forming an insulating protective film. CONSTITUTION:The wiring first metal layer 3 made of aluminum and the second metal layer 5 which is formed of Cr (or Ti, Ti/Cu mixture layer, Cr/Cu mixture layer) and which has good bonding strength with the layer 3 are deposited entirely on a semiconductor substrate 1, a necessary wiring pattern is drawn by photoresist, the layer 5 is etched by dry or wet etching, the layer 3 is then etched with the layer 5 as a mask, thereby forming the desired wiring pattern. Thereafter, an insulating protective film 2 is formed on the overall surface, and a window is opened at the electrode. Subsequently, the thirst meal layer 6 is entirely deposited, the layer 6 is patterned with the photoresist, a solder bump electrode 4 is formed by plating, the photoresist is then removed, the layer 6 is etched with the electrode 4 as a mask, thereby obtaining a semiconductor element with the solder bump electrode.

Description

【発明の詳細な説明】 この発明は、高密度実装基板に半導体素子を７リツプチ
ツプ方式でポンディングするために、半導体基板上に半
田バンプ電極を形成する方法の改良に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for forming solder bump electrodes on a semiconductor substrate in order to bond semiconductor elements to a high-density mounting substrate using the seven-lip chip method.

従来のバンプ電極構造を第１図に示す。この半導体素子
は、半導体基板（１）上にデバイス配線用の金属層（３
）を所定パターンに形成した後、金属層（３）が部分的
に露出する窓を有する絶縁保護膜（２）を形成し、次い
で金属層（３）との密着強度が良好な金属層（５）及び
半田とのぬれ性の良い金属層（６）を順次全面に蒸着し
、その後半田バンプ電極（４）を形成してこの半田バン
プ電極（４）をマスクに各金属層（５）、（６）をエツ
チングにより除去することにより作製してきた。A conventional bump electrode structure is shown in FIG. This semiconductor element has a metal layer (3) for device wiring on a semiconductor substrate (1).
) is formed into a predetermined pattern, an insulating protective film (2) having a window through which the metal layer (3) is partially exposed is formed, and then a metal layer (5) having good adhesion strength to the metal layer (3) is formed. ) and a metal layer (6) with good wettability with solder are sequentially deposited on the entire surface, after which a solder bump electrode (4) is formed, and using this solder bump electrode (4) as a mask, each metal layer (5), ( 6) was produced by removing it by etching.

ところが、この従来方法によると、半田バンプ電極（４
）をエツチング液にさらす回数が多くなるため、半田バ
ンプ電極（４）を侵食する危険度が高くなりひいてはポ
ンディング強度へも影響するという欠点がある。However, according to this conventional method, solder bump electrodes (4
) is exposed to the etching solution more frequently, which increases the risk of corroding the solder bump electrode (4), which in turn affects the bonding strength.

この発明は、上記の様な従来の方法のもつ欠点を除去す
るためになされたもので、絶縁保護膜を形成する前に配
線用金属層との密着強度の良い金属層を所定形状に形成
することにより、半田バンプ電極をエツチング液中に浸
漬する回数を減じることを目的としている。This invention was made in order to eliminate the drawbacks of the conventional methods as described above.Before forming an insulating protective film, a metal layer having good adhesion strength to a wiring metal layer is formed into a predetermined shape. The purpose of this is to reduce the number of times the solder bump electrode is immersed in the etching solution.

以下、この発明の一実施例を図を用いて説明する。An embodiment of the present invention will be described below with reference to the drawings.

第２図において、素子領域が形成された半導体基板（１
）上に、Ａ／からなる配線用の％ｌの金属層（３）と、
Ｃｒ（或いはＴｉ　、　Ｔｉ／Ｃｕ　混合層、Ｃｒ／Ｃ
ｕ混合層）からなり、第１の金属層（３）との密着強度
の良好な第２の金属層（５）を全面蒸着し、フォトレジ
ストを用いて必要な配線パターンを描き、ドライエッチ
又はクエットエッチにより第２の金属層（５）をエツチ
ングした後、この第２の金属層（５）をマスクに＠１の
金稠層（３）をエツチングし、所望の配線パターンを形
喫する。その後、絶縁法ｎ膜（２）を全面に形成し、電
極部に窓をあける。次いで、半田とのぬれ性の良い鋼か
らなる第３の金属層（６）を全面に蒸着し、フォトレジ
ストを用いて第３の金属層（６）の上ｔｉにパターニン
グを行い、メッキによって半田バンプ電極（４）を形成
する。その後、フォトレジストを除去し、第３０金鵡層
（６）を、半田バンプ電以上のようにこの発明によれば
、従来は半田バンプ電極（４）をマスクにして第２及び
第３の金属層（５）、（６）ヲエッチングをしてきたの
が、第３の金属轟けて良いことになるので、半田バンプ
電極（４）をエツチング液に浸漬する回数が減少し、半
田ノ（ンプ電極（４）の腐食を軽減することが可能とな
る。In FIG. 2, a semiconductor substrate (1
), a metal layer (3) of %l for wiring consisting of A/;
Cr (or Ti, Ti/Cu mixed layer, Cr/C
A second metal layer (5) having good adhesion strength to the first metal layer (3) is deposited on the entire surface, a necessary wiring pattern is drawn using photoresist, and dry etching or After etching the second metal layer (5) by Quet etching, the gold oxide layer (3) @1 is etched using the second metal layer (5) as a mask to form a desired wiring pattern. Thereafter, an insulating film (2) is formed on the entire surface, and a window is formed in the electrode portion. Next, a third metal layer (6) made of steel that has good wettability with solder is vapor-deposited over the entire surface, patterned on the top of the third metal layer (6) using photoresist, and soldered by plating. A bump electrode (4) is formed. Thereafter, the photoresist is removed, and the 30th metal layer (6) is applied to the second and third metal layers using the solder bump electrode (4) as a mask. Since the third metal layer etches the layers (5) and (6), the number of times the solder bump electrode (4) is immersed in the etching solution is reduced, and the solder bump electrode (4) is etched in the etching solution. (4) Corrosion can be reduced.

又、第２゛の金属層のサイドエッチ量の制御が容易にで
きる。その上、アルミニツム配線上を全てクロムあるい
はチタンがおおっているため、アルミヒロックによるパ
ッシベーション膜の破壊を抑制する効果も太きい。Further, the amount of side etching of the second metal layer can be easily controlled. Furthermore, since the aluminum wiring is entirely covered with chromium or titanium, it has a great effect in suppressing the destruction of the passivation film due to aluminum hillocks.

【図面の簡単な説明】[Brief explanation of the drawing]

法 第１図は従来の製造方舅を説明するための断面図、第２
図はこの発明の一実施例を示す断面図である。 （１）・・・半導体基板、（２）・・・絶縁保鏝膜、（
３）・・第１の金属層、（４）・・・半田バンプ電極、
（５）・・・第２の金属層、（６）・・・第３の金属層
、 なお、図中同一符号は同一または相当部分を７廖す。Fig. 1 is a sectional view to explain the conventional manufacturing method, Fig. 2 is a sectional view to explain the conventional manufacturing method.
The figure is a sectional view showing an embodiment of the present invention. (1)...Semiconductor substrate, (2)...Insulating trowel film, (
3)...first metal layer, (4)...solder bump electrode,
(5)...Second metal layer, (6)...Third metal layer. Note that the same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] （１）半導体基板上に配線用の第１の金属層と、この第
１の金属層との密着強度が良好な第２の金属層を所定形
状に形成する工程、上記第１及び第２の金属層を有する
半導体基板上に上記第２の金属層が露出する窓を有する
絶縁膜を形成する工程、上記窓部を含んで上記絶縁膜上
に半田とのぬれ性の良い第３の金属層を形成する工程、
上記第３の金属層上に半田バンプ電極を形成する工程を
含む半導体素子の製造方法。(1) A step of forming a first metal layer for wiring and a second metal layer having good adhesion strength with the first metal layer in a predetermined shape on a semiconductor substrate; forming an insulating film having a window through which the second metal layer is exposed on a semiconductor substrate having a metal layer; a third metal layer having good wettability with solder on the insulating film including the window; a process of forming
A method for manufacturing a semiconductor device, including the step of forming a solder bump electrode on the third metal layer.
JP56114140A 1981-07-20 1981-07-20 Manufacture of semiconductor element Pending JPS5815254A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56114140A JPS5815254A (en) 1981-07-20 1981-07-20 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56114140A JPS5815254A (en) 1981-07-20 1981-07-20 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPS5815254A true JPS5815254A (en) 1983-01-28

Family

ID=14630137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56114140A Pending JPS5815254A (en) 1981-07-20 1981-07-20 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS5815254A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172252A (en) * 1983-03-22 1984-09-28 Hitachi Micro Comput Eng Ltd Semiconductor device
JPS6357036U (en) * 1986-09-30 1988-04-16
US5457345A (en) * 1992-05-11 1995-10-10 International Business Machines Corporation Metallization composite having nickle intermediate/interface

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS461973A (en) * 1970-02-06 1971-10-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS461973A (en) * 1970-02-06 1971-10-07

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172252A (en) * 1983-03-22 1984-09-28 Hitachi Micro Comput Eng Ltd Semiconductor device
JPS6357036U (en) * 1986-09-30 1988-04-16
JPH0410990Y2 (en) * 1986-09-30 1992-03-18
US5457345A (en) * 1992-05-11 1995-10-10 International Business Machines Corporation Metallization composite having nickle intermediate/interface
US5719070A (en) * 1992-05-11 1998-02-17 International Business Machines Corporaton Metallization composite having nickel intermediate/interface

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