JPS63289938A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve a metal wire in its cross section geometry for the solution of problems involving humidity-resisting feature, interlayer breakdown strength, resistance presented after wiring, disconnection, etc., and to realize a microstructural, flattened element by a method wherein only a specified quantity of a metal layer is removed in a wet etching process, and then the metal layer is formed into a metal wire in a dry etching process. CONSTITUTION:A wiring metal layer 101 is formed on a semiconductor substrate mounted with an element, a photoresist 102 is applied to the metal layer 101, and the photoresist 102 is subjected to patterning. In a wet etching process, the metal layer 101 is removed by 20-80%, and is next subjected to dry etching for development into a metal wire. For example, a resist 102 is patterned on an Al layer 101 formed 8000-12000Angstrom thick by spattering, and the Al layer 101 is subjected to etching in an etchant that is a water solution of phosphoric acid, nitric acid, and acetic acid, which continues until the Al layer 101 is reduced in thickness by approximately 4000Angstrom . Next, in a dry etching process, unmasked portions are totally removed from the Al layer 101. An SiO2 insulating film 103 is then formed by a vapor growth method.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of forming metal wiring in a semiconductor device. [Prior Art] Metal wiring in a semiconductor device using planar technology is formed into an island shape by photolithography. It is formed by etching using a patterned resist as a mask.

In recent years, the spread of dry etching technology has extended to the process of forming metal wiring, and has greatly contributed to the miniaturization of devices. However, when a metal wiring is formed by this dry etching, the side surface of the metal wiring does not have a steep shape as shown in FIG. 2(a).9 Therefore, as shown in FIG. The coverage of the insulating film formed becomes poor, for example, as shown in Figure 1 408, the uppermost insulating film (
Deterioration of moisture resistance at the part where the metal wiring (hereinafter referred to as "pudge page") cuts the metal wiring, and the part where the upper layer metal wiring 40G crosses over the lower layer metal wiring 401 through the living room insulation film as shown in 409. Q [Problem to be solved by the invention] The gold scrap wiring formed by dry etching has a sharp edge. The above-mentioned problem occurs due to the cross-sectional shape.

The method for manufacturing a semiconductor device of the present invention improves moisture resistance, living room voltage resistance, wiring resistance, and
It is possible to solve problems such as wire breakage and contribute to miniaturization and planarization of elements. a step of coating a photoresist on the metal layer; a step of etching the gold Ii layer by 20% to 80% by wet etching after patterning the photoresist; By dry etching the previous gold IA AM, 14 pieces of gold were obtained. 9 [Embodiment] FIG. 1 shows a process cross-sectional view of an embodiment of the method for manufacturing a semiconductor device according to the present invention. In FIG. Resist 10 on AIA'1101 sputtered to ~12,000
After patterning 2 into an island shape using photolithography, Alalol was wet etched once for 4000 people using a mixed aqueous solution of phosphoric acid, chain acid, and acetic acid as the etching solution, and then this was dry etched to form an island shape. Figure 1(b) shows the state where all the IE has been removed from the areas not masked with resist, and the shoulder part of AI Assignment 101 has been scraped due to side etching during wet etching.■ This is then coated with S
The state in which the iOz insulating film is applied is shown in FIG. 1(C). 1st
As shown in the comparison between FIG. 2(c) and FIG. 2(b), by etching the shoulder portion of the Al wiring, the coverage of the insulating film formed thereon is significantly improved.

FIG. 3 is a cross-sectional view of one embodiment of a semiconductor device manufactured by the method of the present invention. The coverage of the insulation film and the coverage of the underlying metal scrap wiring have been significantly improved.Also, the cross-sectional shape of the Al wiring with etched shoulders also contributes to the flattening of the interlayer insulation film. Therefore, effects such as improved coverage of the upper layer Al wiring at the intersection between the upper layer wiring and the upper layer wiring can be obtained.

The following is an example of the manufacturing method according to the present invention, and the same effect can be obtained not only when the metal wiring is in two layers, but also in multilayer wiring with three or more layers. The same effect can be obtained not only with AI, but also with alloys such as AI.Si, A1.Cu@Si, or AIoTiφSi, and laminated structures of Ti1W and AI.

〔Effect of the invention〕

According to the semiconductor device using the manufacturing method described above, the coverage of Badge Page-r7N is improved and the resistance to ? The reliability of the device can be improved from 9-11 and the like. This is particularly effective for Basson-based films using the reduced pressure vapor phase growth method.

Furthermore, multilayer wiring technology is essential for miniaturization and high integration of semiconductor elements, but when the manufacturing method of the present invention is applied to the lower layer metal wiring of a semiconductor device having two or more layers of metal wiring, The coverage of the living room insulating film formed thereon is improved, and the interlayer constant pressure is improved.

Furthermore, it contributes to the planarization of the interlayer insulating film, and eliminates increases in wiring resistance and disconnections caused by poor coverage of the upper layer metal scrap wiring.

[Brief explanation of drawings]

FIGS. 1(a) to 1(C) are process cross-sectional views of one embodiment of the semiconductor device manufacturing method of the present invention. Section 2 (a) and (b) are cross-sectional views of the conventional manufacturing method. FIG. 3 is a structural cross-sectional view of an embodiment of the semiconductor device according to the manufacturing method of the present invention. FIG. 4 shows a cross section of a semiconductor device manufactured by a conventional manufacturing method. Gold scrap wiring 302.303.402.403... Interlayer insulation 304.404... Passivation film 305,
405... Gate m pole 306.406
・・・Upper layer of metallurgy
) Figure 2 (shi) Third country Figure 4

Claims (1)

[Claims] A step of forming a metal layer for wiring on a semiconductor substrate on which elements have been formed, a step of applying a photoresist on the metal layer, and a step of patterning the photoresist, and then wet etching the metal layer by 20% to 80%. A method for manufacturing a semiconductor device, comprising the steps of etching and further forming metal wiring by dry etching the metal layer.