JPH0227847B2 - - Google Patents

Info

Publication number
JPH0227847B2
JPH0227847B2 JP57068212A JP6821282A JPH0227847B2 JP H0227847 B2 JPH0227847 B2 JP H0227847B2 JP 57068212 A JP57068212 A JP 57068212A JP 6821282 A JP6821282 A JP 6821282A JP H0227847 B2 JPH0227847 B2 JP H0227847B2
Authority
JP
Japan
Prior art keywords
signal
waveform
flop
input
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57068212A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58184823A (ja
Inventor
Takao Tosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57068212A priority Critical patent/JPS58184823A/ja
Publication of JPS58184823A publication Critical patent/JPS58184823A/ja
Publication of JPH0227847B2 publication Critical patent/JPH0227847B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
JP57068212A 1982-04-21 1982-04-21 論理回路 Granted JPS58184823A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57068212A JPS58184823A (ja) 1982-04-21 1982-04-21 論理回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57068212A JPS58184823A (ja) 1982-04-21 1982-04-21 論理回路

Publications (2)

Publication Number Publication Date
JPS58184823A JPS58184823A (ja) 1983-10-28
JPH0227847B2 true JPH0227847B2 (enrdf_load_stackoverflow) 1990-06-20

Family

ID=13367256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57068212A Granted JPS58184823A (ja) 1982-04-21 1982-04-21 論理回路

Country Status (1)

Country Link
JP (1) JPS58184823A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04135043U (ja) * 1991-06-07 1992-12-16 山形日本電気株式会社 信号受信回路

Also Published As

Publication number Publication date
JPS58184823A (ja) 1983-10-28

Similar Documents

Publication Publication Date Title
JPH0227847B2 (enrdf_load_stackoverflow)
JPS5934188Y2 (ja) 信号入力回路
JPS6363215A (ja) チヤタリング除去装置
KR930005934Y1 (ko) D-플립플롭
KR940006928Y1 (ko) 임의의 초기값을 갖는 카운터회로
JPH0437215A (ja) 微分パルス作成回路
JPH0251298B2 (enrdf_load_stackoverflow)
JPS5956845U (ja) カウンタ回路
JPH0691441B2 (ja) 入力同期化回路
JPS6181221U (enrdf_load_stackoverflow)
JPS59189336U (ja) 入力回路
JPH01194710A (ja) パワー・オン・リセット回路
JPH0154886B2 (enrdf_load_stackoverflow)
JPS5893037U (ja) スイツチ回路
JPH05315944A (ja) カウンタ回路
JPS6059186U (ja) １秒タイマ
SWEETON The complete verification of digital system component designs[Ph. D. Thesis]
JPS6284231U (enrdf_load_stackoverflow)
JPS59192741U (ja) Ｃｍｉ符号クロツク抽出回路
JPH04150413A (ja) １／ｎ↓＋↓１分周回路
JPS60134328U (ja) バイナリカウンタ
JPS62103324U (enrdf_load_stackoverflow)
JPH02145822U (enrdf_load_stackoverflow)
JPH0232809B2 (enrdf_load_stackoverflow)
JPS62203521U (enrdf_load_stackoverflow)