JPH0222475B2 - - Google Patents

Info

Publication number
JPH0222475B2
JPH0222475B2 JP20180482A JP20180482A JPH0222475B2 JP H0222475 B2 JPH0222475 B2 JP H0222475B2 JP 20180482 A JP20180482 A JP 20180482A JP 20180482 A JP20180482 A JP 20180482A JP H0222475 B2 JPH0222475 B2 JP H0222475B2
Authority
JP
Japan
Prior art keywords
lines
array
line
fet
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP20180482A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58111192A (ja
Inventor
Ei Ban Basukaaku Maikuru
Ei Horaa Maaku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of JPS58111192A publication Critical patent/JPS58111192A/ja
Publication of JPH0222475B2 publication Critical patent/JPH0222475B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491—Virtual ground arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
JP57201804A 1981-12-24 1982-11-17 仮想接地を用いるメモリアレイ Granted JPS58111192A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/334,304 US4460981A (en) 1981-12-24 1981-12-24 Virtual ground memory
US334304 1999-06-16

Publications (2)

Publication Number Publication Date
JPS58111192A JPS58111192A (ja) 1983-07-02
JPH0222475B2 true JPH0222475B2 (online.php) 1990-05-18

Family

ID=23306598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57201804A Granted JPS58111192A (ja) 1981-12-24 1982-11-17 仮想接地を用いるメモリアレイ

Country Status (2)

Country Link
US (1) US4460981A (online.php)
JP (1) JPS58111192A (online.php)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4594689A (en) * 1984-09-04 1986-06-10 Motorola, Inc. Circuit for equalizing bit lines in a ROM
US4563753A (en) * 1984-09-04 1986-01-07 Motorola, Inc. Circuit for reducing degradation of voltage differential in a memory
US4722075A (en) * 1985-10-15 1988-01-26 Texas Instruments Incorporated Equalized biased array for PROMS and EPROMS
US4802121A (en) * 1986-06-02 1989-01-31 Texas Instruments Incorporated Memory array with partitioned bit lines
US4868790A (en) * 1988-04-28 1989-09-19 Texas Instruments Incorporated Reference circuit for integrated memory arrays having virtual ground connections
JPH023187A (ja) * 1988-06-09 1990-01-08 Toshiba Corp 不揮発性半導体メモリ
US4992980A (en) * 1989-08-07 1991-02-12 Intel Corporation Novel architecture for virtual ground high-density EPROMS
US5023837A (en) * 1989-09-05 1991-06-11 Texas Instruments Incorporated Bitline segmentation in logic arrays
US5027321A (en) * 1989-11-21 1991-06-25 Intel Corporation Apparatus and method for improved reading/programming of virtual ground EPROM arrays
US5020026A (en) * 1989-12-14 1991-05-28 Texas Instruments Incorporated Method and apparatus for reading and programming electrically programmable memory cells
EP0432481A3 (en) * 1989-12-14 1992-04-29 Texas Instruments Incorporated Methods and apparatus for verifying the state of a plurality of electrically programmable memory cells
US5111270A (en) * 1990-02-22 1992-05-05 Intel Corporation Three-dimensional contactless non-volatile memory cell
KR930000899B1 (ko) * 1990-02-24 1993-02-11 현대전자산업 주식회사 다이나믹 램(dram)의 비트선 센스 증폭기의 균형 실현장치
EP0461904A3 (en) * 1990-06-14 1992-09-09 Creative Integrated Systems, Inc. An improved semiconductor read-only vlsi memory
DE69229374T2 (de) * 1991-04-18 2000-01-20 National Semiconductor Corp., Santa Clara Gestapeltes Ätzverfahren für Koppelpunkt-EPROM-Matrizen
US5422842A (en) * 1993-07-08 1995-06-06 Sundisk Corporation Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells
US5959892A (en) * 1997-08-26 1999-09-28 Macronix International Co., Ltd. Apparatus and method for programming virtual ground EPROM array cell without disturbing adjacent cells
JP2004253115A (ja) * 2003-01-30 2004-09-09 Sharp Corp 半導体記憶装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4021781A (en) * 1974-11-19 1977-05-03 Texas Instruments Incorporated Virtual ground read-only-memory for electronic calculator or digital processor
US4281397A (en) * 1979-10-29 1981-07-28 Texas Instruments Incorporated Virtual ground MOS EPROM or ROM matrix
US4312047A (en) * 1980-05-29 1982-01-19 Motorola, Inc. Memory array having improved isolation between sense lines

Also Published As

Publication number Publication date
US4460981A (en) 1984-07-17
JPS58111192A (ja) 1983-07-02

Similar Documents

Publication Publication Date Title
US6407941B1 (en) Segmented non-volatile memory array with multiple sources having improved source line decode circuitry
US5583808A (en) EPROM array segmented for high performance and method for controlling same
US5646886A (en) Flash memory having segmented array for improved operation
KR0179361B1 (ko) 비휘발성 메모리 어레이
US4460981A (en) Virtual ground memory
JP2585348B2 (ja) 不揮発性半導体記憶装置
KR930001283B1 (ko) 반도체 기억장치
JPS6366071B2 (online.php)
US4992980A (en) Novel architecture for virtual ground high-density EPROMS
KR100277268B1 (ko) 반도체 메모리장치
KR960005896B1 (ko) 반도체메모리
US7436716B2 (en) Nonvolatile memory
CN1023431C (zh) 对电可编程存储单元进行读出和编程的方法和装置
US6141277A (en) Semiconductor memory preventing sense amplifier malfunctions due to effects of noise generated in output buffer
JP3280915B2 (ja) 不揮発性半導体記憶装置
US5287315A (en) Skewed reference to improve ones and zeros in EPROM arrays
US7023728B2 (en) Semiconductor memory system including selection transistors
US5392248A (en) Circuit and method for detecting column-line shorts in integrated-circuit memories
US5771192A (en) Bit line reference circuit for a nonvolatile semiconductor memory device
KR950000342B1 (ko) 여분 셀 어레이를 갖는 소거 가능 프로그래머블 리드온리 메모리, 및 이 메모리의 스트레스 시험방법
KR100274440B1 (ko) 가상 접지 메모리 어레이용 열 디코더
JP2537236B2 (ja) 不揮発性半導体メモリ
KR100199359B1 (ko) 고성능을 위한 세그먼트된 eprom 어레이 및 그를 제어하는 방법
KR20010011501A (ko) 메모리셀 어레이의 프로그램 간섭 방지회로
US6272045B1 (en) Nonvolatile semiconductor memory device