JPH0221695B2 - - Google Patents
Info
- Publication number
- JPH0221695B2 JPH0221695B2 JP58059845A JP5984583A JPH0221695B2 JP H0221695 B2 JPH0221695 B2 JP H0221695B2 JP 58059845 A JP58059845 A JP 58059845A JP 5984583 A JP5984583 A JP 5984583A JP H0221695 B2 JPH0221695 B2 JP H0221695B2
- Authority
- JP
- Japan
- Prior art keywords
- time
- circuit
- output
- delay
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010586 diagram Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58059845A JPS59185425A (ja) | 1983-04-05 | 1983-04-05 | デイジタル遅延回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58059845A JPS59185425A (ja) | 1983-04-05 | 1983-04-05 | デイジタル遅延回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59185425A JPS59185425A (ja) | 1984-10-22 |
| JPH0221695B2 true JPH0221695B2 (enExample) | 1990-05-15 |
Family
ID=13124948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58059845A Granted JPS59185425A (ja) | 1983-04-05 | 1983-04-05 | デイジタル遅延回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59185425A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0742951U (ja) * | 1993-12-30 | 1995-08-11 | 梅子 加藤 | 弦楽器の自動調弦装置 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69833340T2 (de) | 1997-07-16 | 2006-10-12 | Nsk Ltd. | Wälzlagereinheit und Gleichlaufgelenk für Räder |
| US6299542B1 (en) | 1998-04-15 | 2001-10-09 | Nsk Ltd. | Constant velocity joint and rolling bearing unit for wheel |
-
1983
- 1983-04-05 JP JP58059845A patent/JPS59185425A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0742951U (ja) * | 1993-12-30 | 1995-08-11 | 梅子 加藤 | 弦楽器の自動調弦装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59185425A (ja) | 1984-10-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0630023A (ja) | セル遅延付加回路 | |
| JPS6357993B2 (enExample) | ||
| EP0551422A4 (en) | Automatic length-reducing audio delay line | |
| JPH05204597A (ja) | メモリ装置 | |
| EP0758826A2 (en) | Packet output device and method | |
| JPH0221695B2 (enExample) | ||
| JP2865314B2 (ja) | パケット通信装置 | |
| JP2757242B2 (ja) | パケット遅延変動制御回路 | |
| JP3190800B2 (ja) | 転送速度切り替え機能付き非同期転送回路 | |
| JP3569592B2 (ja) | 符復号装置 | |
| JP3193202B2 (ja) | Fifo型メモリ | |
| JP2596196Y2 (ja) | デジタルオシロスコ−プのロ−ル表示方式 | |
| JP3154759B2 (ja) | デジタル・フィルタの演算データの遅延方法及び装置 | |
| JPS58218230A (ja) | 遅延時間選定回路 | |
| JP2002050172A (ja) | Fifo制御回路 | |
| JPS5897097A (ja) | 音声信号の時間軸変換装置 | |
| JPS6073694A (ja) | 残響付加装置 | |
| JPH0115221B2 (enExample) | ||
| JPH0331898A (ja) | 音源とシーケンサの接続機構 | |
| JPS5967596A (ja) | 電子楽器の音源装置 | |
| JPH0646083A (ja) | バッファメモリ回路 | |
| JPS5945608A (ja) | 信号処理装置 | |
| JPH0895751A (ja) | Fifoメモリ | |
| JPS5968033A (ja) | 外部装置への出力方法 | |
| JPH0636587A (ja) | 信号遅延メモリ回路 |