JPH0220031B2 - - Google Patents

Info

Publication number
JPH0220031B2
JPH0220031B2 JP56192905A JP19290581A JPH0220031B2 JP H0220031 B2 JPH0220031 B2 JP H0220031B2 JP 56192905 A JP56192905 A JP 56192905A JP 19290581 A JP19290581 A JP 19290581A JP H0220031 B2 JPH0220031 B2 JP H0220031B2
Authority
JP
Japan
Prior art keywords
call
memory
state
relief
operating system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56192905A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5895455A (ja
Inventor
Yoshiharu Oohira
Yasuo Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19290581A priority Critical patent/JPS5895455A/ja
Publication of JPS5895455A publication Critical patent/JPS5895455A/ja
Publication of JPH0220031B2 publication Critical patent/JPH0220031B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/54558—Redundancy, stand-by

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Exchange Systems With Centralized Control (AREA)
JP19290581A 1981-12-02 1981-12-02 再開処理方法 Granted JPS5895455A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19290581A JPS5895455A (ja) 1981-12-02 1981-12-02 再開処理方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19290581A JPS5895455A (ja) 1981-12-02 1981-12-02 再開処理方法

Publications (2)

Publication Number Publication Date
JPS5895455A JPS5895455A (ja) 1983-06-07
JPH0220031B2 true JPH0220031B2 (enExample) 1990-05-07

Family

ID=16298924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19290581A Granted JPS5895455A (ja) 1981-12-02 1981-12-02 再開処理方法

Country Status (1)

Country Link
JP (1) JPS5895455A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2576580B2 (ja) * 1988-04-11 1997-01-29 沖電気工業株式会社 時分割交換機における交信中呼の救済方式

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS593916B2 (ja) * 1979-10-30 1984-01-26 富士通株式会社 再開処理方式

Also Published As

Publication number Publication date
JPS5895455A (ja) 1983-06-07

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