JPH0220023B2 - - Google Patents

Info

Publication number
JPH0220023B2
JPH0220023B2 JP58051894A JP5189483A JPH0220023B2 JP H0220023 B2 JPH0220023 B2 JP H0220023B2 JP 58051894 A JP58051894 A JP 58051894A JP 5189483 A JP5189483 A JP 5189483A JP H0220023 B2 JPH0220023 B2 JP H0220023B2
Authority
JP
Japan
Prior art keywords
clock
phase
window
circuit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58051894A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59178038A (ja
Inventor
Masashi Hirome
Hisashi Morikawa
Susumu Eda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58051894A priority Critical patent/JPS59178038A/ja
Publication of JPS59178038A publication Critical patent/JPS59178038A/ja
Publication of JPH0220023B2 publication Critical patent/JPH0220023B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP58051894A 1983-03-28 1983-03-28 位相同期回路 Granted JPS59178038A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58051894A JPS59178038A (ja) 1983-03-28 1983-03-28 位相同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58051894A JPS59178038A (ja) 1983-03-28 1983-03-28 位相同期回路

Publications (2)

Publication Number Publication Date
JPS59178038A JPS59178038A (ja) 1984-10-09
JPH0220023B2 true JPH0220023B2 (enrdf_load_stackoverflow) 1990-05-07

Family

ID=12899580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58051894A Granted JPS59178038A (ja) 1983-03-28 1983-03-28 位相同期回路

Country Status (1)

Country Link
JP (1) JPS59178038A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2580564B2 (ja) * 1985-12-27 1997-02-12 日本電気株式会社 受信デイスタツフ回路
JPS63229934A (ja) * 1987-03-19 1988-09-26 Fujitsu Ltd タイミングｐｌｌ方式

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5110468A (ja) * 1974-07-15 1976-01-27 Hitachi Ltd Gomidatsusuiki

Also Published As

Publication number Publication date
JPS59178038A (ja) 1984-10-09

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