JPH02192777A - Superconductor transistor - Google Patents

Superconductor transistor

Info

Publication number
JPH02192777A
JPH02192777A JP1012687A JP1268789A JPH02192777A JP H02192777 A JPH02192777 A JP H02192777A JP 1012687 A JP1012687 A JP 1012687A JP 1268789 A JP1268789 A JP 1268789A JP H02192777 A JPH02192777 A JP H02192777A
Authority
JP
Japan
Prior art keywords
insulating layer
region
base region
superconductor
collector region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1012687A
Other languages
Japanese (ja)
Other versions
JP2925566B2 (en
Inventor
Hiroshi Suzuki
博 鈴木
Yoshiaki Nakatani
中谷 吉昭
Tatsuro Usuki
臼杵 辰朗
Masanobu Yoshisato
善里 順信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1012687A priority Critical patent/JP2925566B2/en
Publication of JPH02192777A publication Critical patent/JPH02192777A/en
Application granted granted Critical
Publication of JP2925566B2 publication Critical patent/JP2925566B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To improve operation characteristics by arranging an insulator between a base region and a collector region, making tunnel current flow in an insulating layer, and eliminating a Schottky junction. CONSTITUTION:An insulator 4 is arranged between an emitter region 1 and a collector region 2 composed of superconductor. A collector region 3 composed of degenerated semiconductor of P-type or N-type is arranged, and an insulating layer 5 is interposed between the base region 2 and the collector region 3. The insulating layer is made so thin that tunnel current flows between the regions 2, 3. Since the superconductor 2 and the insulator 4 form a ohmic contact, a Schottky barrier is not generated. As a result, quasi-particle in the base region is injected into the collector region 3 without hindrance, via the insulating layer 5. By eliminating the Schottky junction in this manner, superconducting transistor excellent in operation characteristics can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、超電導体からなるベース領域及びエミッタ領
域と半導体からなるコレクタ領域とを有するベース注入
型の超電導トランジスタに関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a base injection type superconducting transistor having a base region and an emitter region made of a superconductor and a collector region made of a semiconductor.

〔従来の技術〕[Conventional technology]

第3図は従来のベース注入型の超電導トランジスタの構
成を示す模式図であり、超電導体からなるエミッタ領域
1と超電導体からなるベース領域2との間には、絶縁体
4が挾み込まれており、ベース領域2とp型またはn型
の半導体からなるコレクタ領域3とは直接に接合されて
いる。
FIG. 3 is a schematic diagram showing the structure of a conventional base injection type superconducting transistor, in which an insulator 4 is sandwiched between an emitter region 1 made of a superconductor and a base region 2 made of a superconductor. The base region 2 and the collector region 3 made of a p-type or n-type semiconductor are directly connected to each other.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

第4図はこのような構成をなす従来の超電導トランジス
タにおけるエネルギ図である。例えばBi系80に相の
超電導体では30meV、 T R系の超電導体では5
Q m eVのバンドギャプが存在するので、ベース領
域2を構成する超電導体の種類に応じて、ベース領域2
における励起された準粒子(電子または正孔)6はフェ
ルミ準位より高いエネルギ状態にある。
FIG. 4 is an energy diagram of a conventional superconducting transistor having such a configuration. For example, 30 meV for a Bi-based 80-phase superconductor, and 5 meV for a TR-based superconductor.
Since there is a band gap of Q m eV, depending on the type of superconductor constituting the base region 2,
The excited quasiparticle (electron or hole) 6 in is in a higher energy state than the Fermi level.

ところが従来の超電導トランジスタでは、ベース領域2
とコレクタ領域3とが直接に接合されているので、ショ
ットキ接合が形成され、ショットキバリア(界面準位)
Bが発生する。そして両界面に発生するこのショットキ
バリアの高さは50〜100 meV程度であるので、
その高さが高い場合には、準粒子6はこのショットキバ
リアを乗越えられず、ベース領域2からコレクタ領域3
へ注入されない。従って従来の超電導トランジスタでは
、その作動特性に大きな障害があるといういう問題点が
ある。
However, in conventional superconducting transistors, the base region 2
and the collector region 3 are directly connected to each other, a Schottky junction is formed, and a Schottky barrier (interface level)
B occurs. Since the height of this Schottky barrier generated at both interfaces is about 50 to 100 meV,
If the height is high, the quasiparticle 6 cannot overcome this Schottky barrier and moves from the base region 2 to the collector region 3.
is not injected into the Therefore, conventional superconducting transistors have a problem in that their operating characteristics are seriously impaired.

本発明はかかる事情に鑑みてなされたものであり、ベー
ス領域とコレクタ領域との間に薄い絶縁層を介在させる
ことにより、従来のようなショットキ接合を解消し、作
動特性が優れた超電導トランジスタを提供することを目
的とする。
The present invention was made in view of the above circumstances, and by interposing a thin insulating layer between the base region and the collector region, the conventional Schottky junction is eliminated and a superconducting transistor with excellent operating characteristics is created. The purpose is to provide.

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係る超電導トランジスタは、超電導体からなる
ベース領域と半導体からなるコレクタ領域とを有する超
電導トランジスタにおいて、前記ベース領域と前記コレ
クタ領域との間に、トンネル電流が流れ得るような薄い
絶縁層または絶縁体に近い半導体層を設けてあることを
特徴とする。
A superconducting transistor according to the present invention has a base region made of a superconductor and a collector region made of a semiconductor, and a thin insulating layer or It is characterized by having a semiconductor layer close to an insulator.

〔作用〕 本発明の超電導トランジスタにあっては、ベース領域と
コレクタ領域との間にトンネル効果を奏する程度に薄い
絶縁層(または絶縁体に近い半導体層)を設けている。
[Function] In the superconducting transistor of the present invention, an insulating layer (or a semiconductor layer close to an insulator) thin enough to produce a tunnel effect is provided between the base region and the collector region.

そうすると超電導体くベース領域)と絶縁体(絶縁層)
とはオーミック接合となるので、従来のようなショット
キバリアは発生しない。従って、ベース領域内の準粒子
は絶縁層を介して障害なくコレクタ領域内に注入される
Then the superconductor (base region) and insulator (insulating layer)
Since this is an ohmic connection, a Schottky barrier as in the conventional case does not occur. Therefore, quasiparticles in the base region can be injected into the collector region through the insulating layer without any hindrance.

〔実施例〕〔Example〕

以下、本発明をその実施例を示す図面に基づいて説明す
る。
Hereinafter, the present invention will be explained based on drawings showing embodiments thereof.

第1図は本発明に係る超電導トランジスタの構成を示す
模式図であり、図中1,2は夫々超電導体からなるエミ
ッタ領域、ベース領域を示す。該エミッタ領域1とベー
ス領域2との間には、絶縁体4が介在されている。また
図中3は、p型またはn型の縮退半導体からなるコレク
タ領域であり、本発明では、ベース領域2とコレクタ領
域3との間に絶縁層5が介在されている。
FIG. 1 is a schematic diagram showing the structure of a superconducting transistor according to the present invention, in which numerals 1 and 2 respectively indicate an emitter region and a base region made of a superconductor. An insulator 4 is interposed between the emitter region 1 and the base region 2. 3 in the figure is a collector region made of a p-type or n-type degenerate semiconductor, and in the present invention, an insulating layer 5 is interposed between the base region 2 and the collector region 3.

そして本発明において設ける絶縁層5の膜厚は、ベース
領域2.コレクタ領域3間にトンネル電流が流れ得る程
度に設定されている。具体的にはベース領域2を構成す
る超電導体のコヒーレンス長をξとした場合、絶縁層5
の膜厚はξ〜2ξ程度とする。より具体的にはBi系の
超電導体ではそのコヒーレンス長が20〜30人である
ので、Bi系の超電導体をベース領域2として使用する
場合には、絶縁層5の膜厚は30〜50人程度と皮表ば
よい。
The thickness of the insulating layer 5 provided in the present invention is the same as that of the base region 2. It is set to such an extent that a tunnel current can flow between the collector regions 3. Specifically, if the coherence length of the superconductor constituting the base region 2 is ξ, then the insulating layer 5
The film thickness is approximately ξ to 2ξ. More specifically, since the coherence length of a Bi-based superconductor is 20 to 30 nm, when a Bi-based superconductor is used as the base region 2, the thickness of the insulating layer 5 is 30 to 50 nm. The degree and skin surface are fine.

第2図は本発明における超電導トランジスタのエネルギ
図である。本発明ではベース領域2とコレクタ領域3と
の間に絶縁層5を介在させているので、ベース領域2 
(超電導体)と絶縁層5 (絶縁体)との間はオーミッ
ク接合となり、従来のようなショットキバリアは発生せ
ず、準粒子6は容易にベース領域2から絶縁層5内に注
入される。
FIG. 2 is an energy diagram of the superconducting transistor according to the present invention. In the present invention, since the insulating layer 5 is interposed between the base region 2 and the collector region 3, the base region 2
(superconductor) and insulating layer 5 (insulator), an ohmic contact is formed between the superconductor 5 and insulating layer 5, no Schottky barrier occurs as in the conventional case, and quasiparticles 6 are easily injected into insulating layer 5 from base region 2.

そしてトンネル効果を奏する程度の薄さに絶縁層5の膜
厚が設定されているので、絶縁層5内に注入された準粒
子6は絶縁層5を通過してコレクタ領域3へ注入される
Since the thickness of the insulating layer 5 is set to be thin enough to produce a tunnel effect, the quasiparticles 6 injected into the insulating layer 5 pass through the insulating layer 5 and are injected into the collector region 3.

上述した絶縁層5の材質として、絶縁体に極めて近い真
性半導体を使用することができる。そして特に、絶縁層
5及びコレクタ領域3として超格子構造の半導体を使用
する場合には、以下のようにしてベース領域2とコレク
タ領域3との整合を高めることが望ましい。例えばGa
Asの半導体を使用する場合、Ga@及びAs層1層ず
つからなる単位層の厚さを、ベース領域2を構成する超
電導体の1個の結晶の厚さに一致させると、ベース領域
2とコレクタ領域3との両界面の整合が向上する。
As the material of the above-mentioned insulating layer 5, an intrinsic semiconductor which is very similar to an insulator can be used. In particular, when using a semiconductor having a superlattice structure as the insulating layer 5 and the collector region 3, it is desirable to improve the matching between the base region 2 and the collector region 3 in the following manner. For example, Ga
When using an As semiconductor, if the thickness of a unit layer consisting of one Ga@ layer and one As layer is made to match the thickness of one crystal of the superconductor constituting the base region 2, the base region 2 and The alignment of both interfaces with the collector region 3 is improved.

なお上述した実施例においては、横型の超電導トランジ
スタについて説明したが、これに限らず縦型の超電導ト
ランジスタにおいても同様の構成とできることは勿論で
ある。
In the above-described embodiments, a horizontal superconducting transistor has been described, but the present invention is not limited to this, and it goes without saying that a similar structure can be applied to a vertical superconducting transistor.

〔発明の効果] 以上詳述した如く本発明の超電導トランジスタでは、ベ
ース領域とコレクタ領域との間に、トンネル電流が流れ
る程度の薄さである絶縁層またはy1縁体に近い半導体
層を備えているので、従来のようなショットキ接合を避
けることができ、ショットキバリアも発生しない。この
結果、ベース領域からコレクタ領域内に準粒子を容易に
注入することができ、敏速なトランジスタ作動を行うこ
とができる。
[Effects of the Invention] As detailed above, the superconducting transistor of the present invention includes an insulating layer or a semiconductor layer close to the y1 edge that is thin enough to allow tunneling current to flow between the base region and the collector region. Therefore, the conventional Schottky junction can be avoided, and no Schottky barrier occurs. As a result, quasiparticles can be easily injected from the base region into the collector region, allowing rapid transistor operation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る超電導トランジスタの構成を示す
模式図、第2図は同じくそのエネルギ図、第3図は従来
の超電導トランジスタの構成を示す模式図、第4図は同
じくそのエネルギ図である。 1・・・エミッタ領域 2・・・ベース領域 3・・・
コレクタ頭載 4・・・絶縁体 5・・・絶縁層特 許
 出願人   三洋電機株式会社代理人 弁理士   
河 野  登 夫弔 図 弔 図
Figure 1 is a schematic diagram showing the configuration of a superconducting transistor according to the present invention, Figure 2 is its energy diagram, Figure 3 is a schematic diagram showing the configuration of a conventional superconducting transistor, and Figure 4 is its energy diagram. be. 1... Emitter region 2... Base region 3...
Collector head 4... Insulator 5... Insulating layer patent Applicant Sanyo Electric Co., Ltd. agent Patent attorney
Funeral map of Noboru Kono

Claims (1)

【特許請求の範囲】 1、超電導体からなるベース領域と半導体からなるコレ
クタ領域とを有する超電導トランジスタにおいて、 前記ベース領域と前記コレクタ領域との間 に、トンネル電流が流れ得るような薄い絶縁層または絶
縁体に近い半導体層を設けてあることを特徴とする超電
導トランジスタ。
[Claims] 1. In a superconducting transistor having a base region made of a superconductor and a collector region made of a semiconductor, a thin insulating layer or a thin insulating layer through which a tunnel current can flow between the base region and the collector region. A superconducting transistor characterized by having a semiconductor layer that is similar to an insulator.
JP1012687A 1989-01-20 1989-01-20 Superconducting transistor Expired - Fee Related JP2925566B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1012687A JP2925566B2 (en) 1989-01-20 1989-01-20 Superconducting transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1012687A JP2925566B2 (en) 1989-01-20 1989-01-20 Superconducting transistor

Publications (2)

Publication Number Publication Date
JPH02192777A true JPH02192777A (en) 1990-07-30
JP2925566B2 JP2925566B2 (en) 1999-07-28

Family

ID=11812289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1012687A Expired - Fee Related JP2925566B2 (en) 1989-01-20 1989-01-20 Superconducting transistor

Country Status (1)

Country Link
JP (1) JP2925566B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639149A (en) * 1986-06-30 1988-01-14 Fujitsu Ltd Metal base transistor
JPS6332974A (en) * 1986-07-28 1988-02-12 Nippon Telegr & Teleph Corp <Ntt> Superconducting semiconductor junction element and its manufacture
JPS63305573A (en) * 1987-06-05 1988-12-13 Nec Corp Superconductive three-terminal element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639149A (en) * 1986-06-30 1988-01-14 Fujitsu Ltd Metal base transistor
JPS6332974A (en) * 1986-07-28 1988-02-12 Nippon Telegr & Teleph Corp <Ntt> Superconducting semiconductor junction element and its manufacture
JPS63305573A (en) * 1987-06-05 1988-12-13 Nec Corp Superconductive three-terminal element

Also Published As

Publication number Publication date
JP2925566B2 (en) 1999-07-28

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