JPS61242082A - Semiconductor element - Google Patents

Semiconductor element

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Publication number
JPS61242082A
JPS61242082A JP60083896A JP8389685A JPS61242082A JP S61242082 A JPS61242082 A JP S61242082A JP 60083896 A JP60083896 A JP 60083896A JP 8389685 A JP8389685 A JP 8389685A JP S61242082 A JPS61242082 A JP S61242082A
Authority
JP
Japan
Prior art keywords
semiconductor channel
semiconductor
superconducting
source
proximity effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60083896A
Other languages
Japanese (ja)
Inventor
Goji Kawakami
剛司 川上
Hideaki Takayanagi
英明 高柳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP60083896A priority Critical patent/JPS61242082A/en
Publication of JPS61242082A publication Critical patent/JPS61242082A/en
Pending legal-status Critical Current

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To improve the efficiency of gate control while being conformed to the variation of the conductivity of a channel by directly forming source-drain electrodes consisting of a superconductor to a semiconductor channel section and changing effective semiconductor channel length of width thereof by a super conductive proximity effect. CONSTITUTION:Source-drain electrodes 21, 31 composed of a superconductive material are shaped directly (direct contact) to a semiconductor channel 4, and effective semiconductor channel length is shortened by using a superconducting region in a semiconductor formed by a superconducting proximity effect from the source and drain electrodes 21, 31. Accordingly, effective semiconductor channel length is changed by altering the width of the superconducting regions in source and drain sections by the superconductive proximity effect, and the variation (decrease and increase) of semiconductor channel length by the control of a gate 5 and the change (increase and decrease) of the conductivity of a semiconductor channel section are summed up particularly, thus largely improving a current control factor.

Description

【発明の詳細な説明】 〔概 要〕 半導体チャネル部に直接、超伝導体でなるソース、ドレ
イン電極を設け、超伝導近接効果によるソース、ドレイ
ンの超伝導領域により、実効的な半導体チャネルを短縮
し、或いはその領域の幅を変化することにより、半導体
チャネル長が変化するよう(二なし、或いはチャネルの
導電率の増減と該半導体チャネル長の変化(減増)を合
わせ、ゲート制御効率を向上する。
[Detailed Description of the Invention] [Summary] Source and drain electrodes made of a superconductor are provided directly in the semiconductor channel portion, and the effective semiconductor channel is shortened by superconducting regions of the source and drain due to the superconducting proximity effect. Alternatively, by changing the width of the region, the semiconductor channel length can be changed (or, by combining the increase or decrease in the conductivity of the channel with the change (decrease or increase) in the semiconductor channel length, the gate control efficiency can be improved. do.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体素子に係り、特に、ゲート制御効率がよ
く、高速で消費電力の小さい半導体FET素子に関する
ものである。
The present invention relates to a semiconductor device, and particularly to a semiconductor FET device that has good gate control efficiency, high speed, and low power consumption.

〔従来の技術〕[Conventional technology]

第5図〜第6図は従来の半導体FETの素子構造(第5
図、 MES形:第6図、 MIS形)を示す。
Figures 5 and 6 show the element structure of a conventional semiconductor FET (Figure 5).
Fig. 6 shows the MES type; Fig. 6 shows the MIS type.

第5図のMES形では5のゲート電極のゲート電圧の印
加(二よるチャネル用半導体層4での空乏層4αの厚さ
の制御によりソース/ドレイン(2b15b)間の電流
を制御する。なお、1αは半導体基板、2α、6αはソ
ース、ドレイン電極である。第6図のMIS形ではゲー
ト電圧の印加によりチャネル部のキャリア濃度を増減さ
せてソース/ドレイン(2b75 b )間の電流を制
御する。なお第6図(二おいて、第5図と対応部には同
一符号で指示してあり、6はMIS用絶用膜縁膜bは半
導体基板である。しかしこれらにおいてソース及びドレ
インは半導体(通常は高濃度)または常伝導電極であり
、チャネル部の半導体の長さ4r:斐えることはなかっ
た。
In the MES type shown in FIG. 5, the current between the source/drain (2b15b) is controlled by applying the gate voltage to the gate electrode 5 (by controlling the thickness of the depletion layer 4α in the channel semiconductor layer 4). 1α is a semiconductor substrate, 2α and 6α are source and drain electrodes. In the MIS type shown in Fig. 6, the current between the source and drain (2b75 b ) is controlled by increasing or decreasing the carrier concentration in the channel part by applying a gate voltage. .In FIG. 6 (2), parts corresponding to those in FIG. (usually high concentration) or a normal conduction electrode, and the length of the semiconductor in the channel portion was 4r: There was no change.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来Cニオいてはゲー)Cよる電流制御の効率5:gい
てなお十分でなかった。本発明の目的はゲートによる電
流制御の高効率化を図ることにある。
Conventionally, the efficiency of current control using C was still insufficient, even though the efficiency was 5:g. An object of the present invention is to improve the efficiency of current control by a gate.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、超伝導材料でなるソース及びドレイン電極を
半導体チャネルに直接形成しく直接接触している)、こ
のソース及びドレイン電極から超伝導近接効果により形
成される半導体中での超伝導領域を用いて実効的な半導
体チャネル長を短縮すること、及びこの近接効果領域の
増減をFETの電流制御(二合わせ用いることを最も主
要な特徴とする。
The present invention uses a superconducting region in a semiconductor that is formed from the source and drain electrodes by the superconducting proximity effect (the source and drain electrodes made of a superconducting material are formed directly in the semiconductor channel and in direct contact with the semiconductor channel). The most important features are shortening the effective semiconductor channel length and controlling the FET current to increase or decrease the proximity effect region.

〔作 用〕[For production]

本発明によれば、超伝導近接効果によるソース及びドレ
イン部における超伝導領域の幅を変化することにより、
実効的な半導体チャネル長が変化する。特に、ゲート制
御(二よる半導体チャネル長の変化(減、増)と、半導
体チャネル部の導電率の変化(増、減)を合わせること
により、電流制御率の大幅な向上が可能となる。
According to the present invention, by changing the width of the superconducting region in the source and drain parts due to the superconducting proximity effect,
The effective semiconductor channel length changes. In particular, by combining changes (decrease, increase) in the semiconductor channel length due to gate control (2) and changes (increase, decrease) in the conductivity of the semiconductor channel portion, it is possible to significantly improve the current control rate.

〔実施例〕〔Example〕

第1図〜第3図は本発明の実施例1〜3:二おける半導
体素子の断面図で、半導体チャネル部に直接超伝導材料
からなるソース及びドレイン電極21 、51が形成さ
れている。超伝導体が常伝導体に接している場合、その
界面では超伝導電子と常伝導電子の相互拡散が生じる。
1 to 3 are cross-sectional views of semiconductor devices in Examples 1 to 3:2 of the present invention, in which source and drain electrodes 21 and 51 made of a superconducting material are formed directly in the semiconductor channel portion. When a superconductor is in contact with a normal conductor, mutual diffusion of superconducting electrons and normal conducting electrons occurs at the interface.

これは超伝導近接効果として知られているものである。This is known as the superconducting proximity effect.

第4図はこの効果によるチャネル部近接の超伝導ペアポ
テンシャル分布(超伝導電子数に相当)tホしたもので
ある。即ちもとの半導体領域りのうち超伝導電極近傍ら
、l(を部分が近接効果により超伝導体となる。この近
接効果領域の大きさは半導体中の超伝導拡散長ξユによ
ってきまり、自由電子モデルでは、キャリア濃度の立方
根とキャリア移動度の平方根C二比例し、キャリア有効
質量の平方根に逆比例する。ξユは半導体材料によって
異なるが、l5As。
FIG. 4 shows the superconducting pair potential distribution (corresponding to the number of superconducting electrons) near the channel portion due to this effect. In other words, the portion of the original semiconductor region near the superconducting electrode becomes a superconductor due to the proximity effect. The size of this proximity effect region is determined by the superconducting diffusion length ξ in the semiconductor, and is free In the electronic model, the cube root of carrier concentration and the square root of carrier mobility C are proportional to each other, and inversely proportional to the square root of carrier effective mass.

Iルsbのような狭バンドギヤツプ高電子移動度化合物
半導体では比較的大きく、0.1〜0.3ミクロン程度
である。一方近接効果≦二より超伝導とみなせる領域ら
、ldは半導体、/超伝導体界面での条件即ち超伝導電
子の半導体中への遷移の容易さ(第4図におけるΔ。の
大きさ:遷移確立=Δ0/Δ、)にも関係する。即ち同
じξユでもΔ。の大きい方から、ldは長い。このため
半導体/超伝導体界面を清浄化し、場合によっては半導
体表面を高ドープ化して、超伝導電子の遷移を大きくす
ることが有効である。通常1..1dはξ7のオーダか
らその数倍の長さと考えてよい。本発明では近接効果に
より半導体の一部を超伝導体(二変え、実効的な半導体
チャネル長を短縮すること、及びこの長さの変化による
半導体実効長の増減をチャネル部の導電率の変化ととも
(;用いる。
In a narrow bandgap high electron mobility compound semiconductor such as ILSB, it is relatively large, on the order of 0.1 to 0.3 microns. On the other hand, since the proximity effect ≦ 2, the region can be regarded as superconducting, ld is the condition at the semiconductor/superconductor interface, that is, the ease of transition of superconducting electrons into the semiconductor (the size of Δ in Fig. 4: transition It is also related to probability=Δ0/Δ,). In other words, even with the same ξU, Δ. ld is long from the larger one. For this reason, it is effective to clean the semiconductor/superconductor interface and, in some cases, highly dope the semiconductor surface to increase the transition of superconducting electrons. Usually 1. .. 1d can be considered to be on the order of ξ7 or several times longer. In the present invention, by converting a part of the semiconductor into a superconductor (2) due to the proximity effect, the effective semiconductor channel length can be shortened, and the increase or decrease in the semiconductor effective length due to this change in length can be interpreted as a change in the conductivity of the channel part. Tomo (; used.

まず第1因の接合形またはMES形における実施例につ
いて詳細に説明する。1αは半絶縁性またはP形半導体
基板、21.31は超伝導電極である。
First, an embodiment of the junction type or MES type of the first factor will be described in detail. 1α is a semi-insulating or P-type semiconductor substrate, and 21.31 is a superconducting electrode.

4はル形(チャネル用)半導体層、41はゲート用P形
Cp−rb接合用)半導体層(MES形の場合はこの層
は無い)、4aは空乏層領域、5はデート電極である。
4 is an R-type (for channel) semiconductor layer, 41 is a P-type (for gate Cp-rb junction) semiconductor layer (this layer is not present in the case of MES type), 4a is a depletion layer region, and 5 is a date electrode.

元の半導体層の長さはLであるか、第4図に示すように
超伝導近接効果により1..1d、部が超伝導となり実
際の半導体チャネル長は1.となる。例えば4として、
n形1nAz(Dlo” 〜10”cm−’のものを用
いると、4.2にで移動度は20000〜5000 a
n>”/ V、程度であり、輸は0.1 pm −0,
2μmである。ル形1rLAzでは半導体/金属界面バ
リアは負の値(バリア無し)であるため、半導体表面の
清浄化により大きな遷移確率が得られるためら、ldは
0.5〜1μ扉程度となり、Lが1μm以上の場合でも
容易にサブミクロンの短チャネルFETを形成すること
ができる。
The length of the original semiconductor layer is either L or 1.0 due to the superconducting proximity effect as shown in FIG. .. 1d becomes superconducting, and the actual semiconductor channel length is 1. becomes. For example, as 4,
If an n-type 1nAz (Dlo"~10"cm-') is used, the mobility is 4.2 and the mobility is 20000~5000a.
n>”/V, and the import is 0.1 pm −0,
It is 2 μm. In the case of L type 1rLAz, the semiconductor/metal interface barrier has a negative value (no barrier), so a large transition probability can be obtained by cleaning the semiconductor surface, so ld is about 0.5 to 1 μm, and L is 1 μm. Even in the above case, a submicron short channel FET can be easily formed.

第2図は前実施例と類似の素子構造であるが、ゲート電
極としてオーミック電極を用いたものである。たとえば
チャネル用半導体層4としてル形JnSAk用いる。こ
の場合は半導体/金属界面バリアは〜0.17#Vと正
の有限値を持っため(第2図(5)のイへ超伝導電子の
半導体中への遷移は抑制される。とく(ニキャリア濃度
がさほど大きくない場合はΔ0(第4図)が小さく1.
.1.は零に近い。
FIG. 2 shows an element structure similar to that of the previous embodiment, except that an ohmic electrode is used as the gate electrode. For example, as the channel semiconductor layer 4, a square type JnSAk is used. In this case, the semiconductor/metal interface barrier has a positive finite value of ~0.17#V (see Figure 2 (5)), so the transition of superconducting electrons into the semiconductor is suppressed. When the carrier concentration is not very high, Δ0 (Figure 4) is small and 1.
.. 1. is close to zero.

ここでソース、ドレイン超伝導電極に対し正のバイアス
を半導体4に印加するか、またはゲート電極から電子を
注入すると(第2図(ト)の口)、超伝導電子の遷移が
増加し1. 、1cLを大きくすることができる。それ
により、半導体チャネル長が変化する。
If a positive bias is applied to the semiconductor 4 with respect to the source and drain superconducting electrodes, or if electrons are injected from the gate electrode (see the opening in FIG. 2 (G)), the transition of superconducting electrons increases.1. , 1 cL can be increased. This changes the semiconductor channel length.

次に第3図に示したMIS形素子の例(二ついて説明す
る。1hは半導体基板、6はゲート用(Mis用)絶縁
膜である。もとの半導体層の長さはLである。
Next, an example of the MIS type element shown in FIG. 3 (two will be explained). 1h is a semiconductor substrate, 6 is an insulating film for a gate (for Mis). The length of the original semiconductor layer is L.

ゲート/ソース間または基板間に電圧が印加されていな
い場合または電圧印加(逆電圧)によりチャネル部のキ
ャリア#度設零もしくは非常に小さくした場合はl、 
、 l、はほとんど零である(Off状態)。次にゲー
ト/ソース間に動作方向の電圧を加えると(0ル状態)
、表面反転層が形成され(キャリア濃度増大)、チャネ
ルコンダクタンスが増加する。しかしこの場合はさらに
キャリア濃度増大(二よるξ、の増加が生じる。従って
超伝導近接効果によりl、 、 l、1が有限の値を持
つようになり、実際の半導体チャネル幅はLから!、に
減少する。即ちl、、l、部分は超伝導となり(抵抗は
零)、かつチャネル部の伝導率は大きい。この二つの効
果により、FETの電流を増加させる事が出来るため、
ゲートによる制御効率を大幅に増大させることが出来る
。具体例として、半導体基板11JにP形1nAsを用
いたもので説明する。p形IrLAzでは、表面に自然
反転したル形チャネル層が形成されている。ゲート用絶
縁膜全表面に形成した場合、このチャネルは維持される
かまたは固定電荷によりチャネルは消滅する。前者の場
合はゲートに負のバイアス印す口によりチャネルを消滅
させる事ができる。いずれもoff状態に相当しキャリ
アはなくら、l(tは零、チャネルコンダクタンスも零
である。これにゲートバイアスを正方向電子ガスである
場合C;は、キャリアa度の増大と   □ともに、電
子移動度の増大が生じる。これらの効果により軸が増大
し、1. 、1ctの増大、!、の減少が生じる。この
実施例ではt、の減少、チャネルコンダクタンスの増加
の二つの効果により電流が制御出来るため、ゲート制御
効率?大幅に増大させる事ができる。
When no voltage is applied between the gate and source or between the substrate, or when the carrier number in the channel part is set to zero or very small by applying a voltage (reverse voltage), l,
, l, are almost zero (Off state). Next, when applying a voltage in the operating direction between the gate and source (0 state)
, a surface inversion layer is formed (carrier concentration increases), and channel conductance increases. However, in this case, the carrier concentration further increases (ξ due to 2). Therefore, due to the superconducting proximity effect, l, , l, 1 has a finite value, and the actual semiconductor channel width is from L! In other words, the l, l part becomes superconducting (resistance is zero), and the conductivity of the channel part is large.These two effects make it possible to increase the FET current, so
Control efficiency by gates can be greatly increased. As a specific example, a semiconductor substrate 11J using P-type 1nAs will be explained. In p-type IrLAz, a naturally inverted channel layer is formed on the surface. When formed over the entire surface of the gate insulating film, this channel is maintained or disappears due to fixed charges. In the former case, the channel can be eliminated by applying a negative bias to the gate. Both correspond to the off state, there are no carriers, l(t is zero, and the channel conductance is also zero.If the gate bias is a positive electron gas, C; increases as the carrier a degree increases, and □ An increase in electron mobility occurs. These effects cause an increase in the axis, an increase in 1., 1ct, and a decrease in !. In this example, the current Since gate control efficiency can be controlled, gate control efficiency can be greatly increased.

以上、本発明についてゲート電極を設けてゲート制御す
る例を示したが、半導体に対する光、或いは電子ビーム
等の照射等C:よる半導体チャネル部への制御により、
上記と同様な素子の制御が可能である。また、これはデ
ィテクタとしての使用も可能である。
In the above, an example of gate control by providing a gate electrode has been shown in the present invention, but by controlling the semiconductor channel portion by irradiating the semiconductor with light, electron beam, etc.,
Control of elements similar to those described above is possible. It can also be used as a detector.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明における半導体素子では、
超伝導近接効果によりチャネル長を短縮させゲート制御
効率を向上させること、半導体チャネルの伝導率の増加
と近接効果によるチャネル長の減少を同時に用いること
により、ゲート制御効率の大幅な改良を図ることが出来
る。また、いわゆる半導体納会超伝導素子龜;比べると
、本発明の素子は超伝導電極間隔を長くすることができ
る。
As explained above, in the semiconductor element of the present invention,
By shortening the channel length using the superconducting proximity effect and improving the gate control efficiency, it is possible to significantly improve the gate control efficiency by simultaneously increasing the conductivity of the semiconductor channel and reducing the channel length due to the proximity effect. I can do it. In addition, compared to so-called semiconductor-based superconducting devices, the device of the present invention allows for a longer distance between superconducting electrodes.

これは素子の作製を容易1:するととも(二、素子特性
の歩留り向上に有利であり、集積化の際には重要である
This facilitates device fabrication (1) and is advantageous in improving the yield of device characteristics (2), which is important in integration.

【図面の簡単な説明】[Brief explanation of the drawing]

′s1図は本発明の実施例1の接合形またはMES形半
形半導体子の断面図、第2図(イ)は本発明の実施例2
のオーミック電極による素子制御における素子断面図及
び第2図(5)はバンド構造図、第3図は本発明の実施
例3のMis形半導体素子の断面図、第4図は超伝導近
接効果:;よる超伝導ペアポテンシャル図、第5図及び
第6図は従来及び他の従来の半導体FETの素子構造を
示T図である。 1α、16・・・半導体基板、2α、3α・・・ソース
及びドレイン電極、2b、5b・・・ソース及びドレイ
ン(用半導体層)、4・・・チャネル用半導体層、21
 、31・・・超伝導電極、41・・・pn接合用半導
体層、5・・・ゲート電極、6・・・MIS用絶用膜縁
膜・・・超伝導電極間隔(チャネル用半導体領域へら、
lct・・・近接効果による超伝導領域、l、・・・実
効チャネル長(l、=r、−t、−t、) 特許出願人  日本電信電話株式会社 代理人 弁理士 玉蟲久五部(外2名)実施例3の断面
図 第3図 超伝導体   半 導 体   超伝導体超イ云導近授
りカ果による超伝導ベアボテンシャ11図第 4 図 ソースを極     ケートv槓 従来のFETの断面図 第5図 他の従来のFETの断面図 第6図
Figure 's1 is a sectional view of a junction type or MES type half-shaped semiconductor device according to Embodiment 1 of the present invention, and Figure 2 (A) is a sectional view of Embodiment 2 of the present invention.
2(5) is a band structure diagram, FIG. 3 is a sectional view of the Mis-type semiconductor device of Example 3 of the present invention, and FIG. 4 is a superconducting proximity effect: FIGS. 5 and 6 are T diagrams showing element structures of conventional and other conventional semiconductor FETs. 1α, 16... Semiconductor substrate, 2α, 3α... Source and drain electrodes, 2b, 5b... Source and drain (semiconductor layer), 4... Semiconductor layer for channel, 21
, 31... Superconducting electrode, 41... Semiconductor layer for pn junction, 5... Gate electrode, 6... Insulating film for MIS... Superconducting electrode spacing (semiconductor region spacing for channel) ,
lct...superconducting region due to proximity effect, l,...effective channel length (l, = r, -t, -t,) Patent applicant Nippon Telegraph and Telephone Corporation agent Patent attorney Gobe Tamamushi (external) 2 people) Cross-sectional view of Example 3 Figure 3 Superconductor Semiconductor Superconductor Bare Botentia due to the effects of superconductivity Figure 5. Cross-sectional view of another conventional FET Figure 6

Claims (1)

【特許請求の範囲】 1、半導体チャネル部に直接、超伝導体でなるソース及
びドレイン電極を配設し、該ソース及びドレイン電極か
ら超伝導近接効果により形成される半導体チャネル部中
での超伝導領域により、半導体チャネル長が短縮されて
なることを特徴とする半導体素子。 2、半導体チャネル部に直接、超伝導体でなるソース及
びドレイン電極を配設し、該ソース及びドレイン電極か
ら超伝導近接効果により形成される半導体チャネル部中
での超伝導領域により、半導体チャネル長が短縮される
とともに、超伝導近接効果による前記超伝導領域の幅を
変化することにより半導体チャネル長が変化するように
したことを特徴とする半導体素子。 3、半導体チャネル部に直接、超伝導体でなるソース及
びドレイン電極を配設し、さらに両電極間にゲート電極
を設け、ゲート制御による半導体/超伝導体界面の電子
バリアの増減で、該ソース及びドレイン電極から超伝導
近接効果により形成される半導体チャネル部中での超伝
導領域を縮伸することにより、半導体チャネル長が変化
するようにしたことを特徴とする半導体素子。 4、半導体チャネル部に直接、超伝導体でなるソース及
びドレイン電極を配設し、さらに両者間にゲート電極を
設け、ゲート制御により半導体チャネル部の導電率が増
減するようになし、該導電率の増減に合わせて、該ソー
ス及びドレイン電極から超伝導近接効果により形成され
る半導体チャネル部中での超伝導領域の伸縮が生じ、半
導体チャネル部の導電率の増減に合わせて半導体チャネ
ル長が減増するようにしたことを特徴とする半導体素子
[Claims] 1. Source and drain electrodes made of a superconductor are provided directly in the semiconductor channel portion, and superconductivity in the semiconductor channel portion is formed from the source and drain electrodes by the superconducting proximity effect. A semiconductor device characterized in that a semiconductor channel length is shortened by a region. 2. Source and drain electrodes made of a superconductor are provided directly in the semiconductor channel portion, and the semiconductor channel length is increased by the superconducting region in the semiconductor channel portion formed from the source and drain electrodes by the superconducting proximity effect. 1. A semiconductor device characterized in that a semiconductor channel length is changed by changing the width of the superconducting region due to a superconducting proximity effect. 3. Source and drain electrodes made of a superconductor are provided directly in the semiconductor channel region, and a gate electrode is provided between the two electrodes. and a semiconductor device characterized in that a semiconductor channel length is changed by contracting and stretching a superconducting region in a semiconductor channel portion formed from a drain electrode by a superconducting proximity effect. 4. Source and drain electrodes made of a superconductor are provided directly on the semiconductor channel portion, and a gate electrode is provided between the two, so that the conductivity of the semiconductor channel portion can be increased or decreased by gate control, and the conductivity can be increased or decreased by controlling the gate. As the conductivity of the semiconductor channel increases, the superconducting region in the semiconductor channel formed from the source and drain electrodes due to the superconducting proximity effect expands and contracts, and the semiconductor channel length decreases as the conductivity of the semiconductor channel increases. 1. A semiconductor device characterized in that the number of semiconductor devices increases.
JP60083896A 1985-04-19 1985-04-19 Semiconductor element Pending JPS61242082A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60083896A JPS61242082A (en) 1985-04-19 1985-04-19 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60083896A JPS61242082A (en) 1985-04-19 1985-04-19 Semiconductor element

Publications (1)

Publication Number Publication Date
JPS61242082A true JPS61242082A (en) 1986-10-28

Family

ID=13815390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60083896A Pending JPS61242082A (en) 1985-04-19 1985-04-19 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS61242082A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63143870A (en) * 1986-12-08 1988-06-16 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS63228696A (en) * 1987-03-18 1988-09-22 Hitachi Ltd Electronic device
JPS6486575A (en) * 1987-06-17 1989-03-31 Hitachi Ltd Superconducting device
JPH0294678A (en) * 1988-09-30 1990-04-05 Toshiba Corp Superconducting device
JP2005294782A (en) * 2004-03-31 2005-10-20 Takeshi Awaji Semiconductor superconductivity element

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57176781A (en) * 1981-04-22 1982-10-30 Toshiba Corp Superconductive device
JPS59103389A (en) * 1982-12-04 1984-06-14 Nippon Telegr & Teleph Corp <Ntt> Superconductive element and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57176781A (en) * 1981-04-22 1982-10-30 Toshiba Corp Superconductive device
JPS59103389A (en) * 1982-12-04 1984-06-14 Nippon Telegr & Teleph Corp <Ntt> Superconductive element and manufacture thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63143870A (en) * 1986-12-08 1988-06-16 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS63228696A (en) * 1987-03-18 1988-09-22 Hitachi Ltd Electronic device
JPS6486575A (en) * 1987-06-17 1989-03-31 Hitachi Ltd Superconducting device
JPH0294678A (en) * 1988-09-30 1990-04-05 Toshiba Corp Superconducting device
JP2005294782A (en) * 2004-03-31 2005-10-20 Takeshi Awaji Semiconductor superconductivity element

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