JP2701095B2 - Semiconductor coupled superconducting element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting element having a semiconductor at a junction, that is, a semiconductor coupled superconducting element having a superconductor-semiconductor-superconductor coupling.

[0002]

2. Description of the Related Art Since the invention of the tunnel type Josephson device, much research has been conducted on superconducting three-terminal devices corresponding to bipolar transistors and field effect transistors (FETs) in semiconductors. Among them, many attempts have been made for semiconductor-coupled superconducting elements due to the possibility of three-terminal operation by electrical control of semiconductors, but none of them has been practically used. This was mainly due to lack or small gain of the transistor.
Hereinafter, this will be described with a specific example.

[0003] Typical semiconductor-coupled superconducting elements realized so far include those using p-type InAs,
Some use p-type Si.

A semiconductor-coupled superconducting device using p-type InAs is disclosed by H. Takayanagi and T. Kawakami.
"Superconducting Proximity Effect in the Native I
nversion Layer on InAs ", Physical R
eview Letters 54, (1985), 2449, or H. Takayanagi
And "Planar-Type InAs-Coupl" by T. Kawakami
ed Three-Terminal Superconducting Devices ", Digest of Technical Papers, 98, 1985 Intern
ational Electron Device Meeting, Washington DC
And a paper entitled "MIS-type InAs superconducting three-terminal device" by Yanagi and Kawakami, as disclosed in IEICE Technical Report SCE 86-23 (1986).

Further, as a semiconductor-coupled superconducting element using p-type Si, there are T. Nishino, M. Miyake, and Y. Harada.
And U. Kawabe "Three-Terminal Superconduc
tingDevice Using a Si Single-Crystal Film ", IEEE Electron Devices Letters 6, (198
5), 297.

FIG. 18 shows a cross-sectional structure of a semiconductor-coupled superconducting element using p-type InAs. The source 3 and the drain 4 are made of Nb which is a superconductor, and a superconducting current flows between the source 3 and the drain 4 via the n-type natural inversion layer 2. This superconducting current is converted to MIS (metal-insulator-semic
Onductor) not controlled by the gate voltage V _g applied to form the gate 6, since it corresponds to the FET in the semiconductor, also referred to as FET type superconducting transistor. FIG.
FIG. 9 shows current-voltage characteristics (source-drain current _IDS vs. source-drain voltage _VDS ) of this device. 7
Is the characteristic when the gate voltage is zero, 8 is the characteristic when the gate voltage is applied, and the point where the load line 9 intersects the two characteristics.
That is, A and B are operating points for turning on and off the transistor. Therefore, the voltage difference V between A and B
_out becomes the output. On the other hand, since the input is V _g , the gain G of this transistor is G = V _out / V _g . Therefore, this G is specifically obtained.

The current-voltage characteristic 7 shown in FIG. 19 is composed of a superconducting state (V _DS = 0) and a normal conducting state in which a resistance is generated. In the former, the maximum value of the superconducting current flowing is determined by the critical current I _C. , referred to as resistance in the latter the normal conductive resistance R _N.
If in such a superconductive element, in which almost the product I _C R _N of I _C and R _N constant, was used Nb as the superconducting electrode, I
_C R _N is about 1 mV. This also applies to state 8 with the gate voltage applied, and in state 1 now I _C = 100 μA, R
Assuming that _N = 10Ω, in state 8, for example, I _C = 1 μA,
R _N = 1 kΩ. That is, I _C is changed by about 100 μA depending on the gate voltage. When the sensitivity S of I _C with respect to V _g is defined as S = dI _C / dV _g , in the device using the p-type InAs inversion layer of FIG. 18, S = 10 ⁻⁴ A.
In the device using / V and Si, it was measured that S = 10 ⁻³ A / V. Therefore, it can be seen that a device using InAs requires a gate voltage of 1 V and a device using Si requires a gate voltage of 0.1 V to change I _C by about 100 μA. On the other hand, in this case, the output voltage V _out is V _out = 100 μ
It can be expressed as A × _RL . A load resistor R _L representing the load line 3 in FIG. 19, the product of the capacitance C _g with the gate portion is a factor that determines the switching speed of the device, R _L can not be very large. Therefore, for example, if R _L = 1 kΩ, the above-mentioned gain G = V _out / V _g becomes 1/10 in the element using InAs and 1 in the element using Si. Finally gain the R _L to 10 times the 10kΩ of R _N are each 1 and 10
However, this cannot make use of the high speed of the superconducting element. Thus, it can be seen that a large gain cannot be obtained with this type of superconducting transistor.

The reason lies in the operation principle of the FET type superconducting transistor described above. This will be described in comparison with the operation of a normal semiconductor FET. FIG. 20 shows current-voltage characteristics (source-drain current _IDS vs. source-drain voltage _VDS ) of a normal semiconductor FET. The current-voltage characteristic has strong nonlinearity, and the source / drain current becomes substantially constant above a certain source / drain voltage. This is referred to as a saturation region. By using this saturation region, as shown in the figure, if two operating points A and B are taken corresponding to on and off of the gate voltage, the voltage between the two operating points is obtained. The difference, i.e., the output, can be large, and as a result, the gain is also large. On the other hand, in the superconducting transistor, the operating current and the voltage are each 1 as described above.
Since it is as small as about 00 μA and 0.1 V, the saturation region cannot be reached, and therefore, the operation using the saturation region cannot be used. Therefore, the gain is smaller than that of the semiconductor FET.

[0009]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems in the conventional superconductor-semiconductor-superconductor coupling element, that is, the problem that the gain is small for practical use, and that the gain is large. An object is to realize a superconducting three-terminal element having excellent characteristics.

More specifically, one of the objects of the present invention is to provide a semiconductor-coupled superconductor having a MIS type gate structure in which a gate electrode for controlling superconducting current flowing in a two-dimensional electron gas is divided into two on a semiconductor. It is to provide a conductive element.

Another object of the present invention is to provide a narrow portion in a two-dimensional electron gas for controlling a superconducting current flowing in a two-dimensional current gas, and further to provide a MIS on a semiconductor.
It is an object of the present invention to provide a semiconductor-coupled superconducting device having a gate structure.

[0012]

SUMMARY OF THE INVENTION The present invention relates to a FET type superconducting transistor in which two-dimensional electron gas is coupled in a semiconductor, wherein the gate structure of the FET superconducting transistor is divided into two, or two-dimensional electron gas. It has a narrow portion inside and a normal MIS type gate on the semiconductor, and the most important feature is that the current-voltage characteristics between source and drain can be controlled discontinuously by the gate voltage. And A conventional superconducting transistor has a gate structure or a narrow portion in a two-dimensional electron gas. In operation, a conventional superconducting transistor continuously controls current-voltage characteristics. On the other hand, the present invention is different in that the control is discontinuous.

The structure of the present invention is as follows. That is, the present invention provides a two-dimensional electron gas (1) formed on the interface of the junction of different semiconductors (15, 17) or the surface natural inversion layer (32) of the MIS junction (36-35-31).
6, 32), two superconducting electrodes (13, 14), (33, 34) in ohmic contact with the semiconductor on which the two-dimensional electron gas (16, 32) is formed, and In a semiconductor-coupled superconducting element having a gate electrode (20, 36) for controlling a superconducting current flowing in a two-dimensional electron gas (16, 32) between superconducting electrodes (13, 14) and (33, 34). Wherein the gate electrode (20, 36) has a MIS type gate structure (20-19-18, 36-35-31) divided into two on a semiconductor (18, 31). It has a configuration as a superconducting element. Alternatively, different semiconductors (5,
7) Bonding interface or MIS bonding (66-65-6)
The two-dimensional electron gas (46, 62) formed on the surface natural inversion layer (62) of 1) and the two-dimensional electron gas (46, 62).
Two superconducting electrodes (43, 44) and (63, 64) in ohmic contact with the semiconductor on which 62) is formed.
And the two superconducting electrodes (43, 44), (63, 6).
And (4) a semiconductor-coupled superconducting device having a gate electrode (50, 66) for controlling a superconducting current flowing in the two-dimensional electron gas (46, 62).
6, 62) and a narrow portion (51, 71) in the MIS gate structure (50-61) on the semiconductor (48, 61).
49-48, 66-65-61).

[0014]

Embodiment 1 FIGS. 1 and 2 are views for explaining a first embodiment of the present invention, in which 11 is an InP substrate, 12 is non-doped InAlAs, 13 and 14 are superconducting electrodes, and source and drain. , 15 are non-doped InGaAs, 16
Is a two-dimensional electron gas formed on the 15 side of the interface between 15 and 17, 17 is a non-doped InAlAs, and 18 is an n-type
nAlAs, 19 is non-doped InAlAs, 20 is a metal gate electrode, and 19, 20 constitute a MIS gate. FIG. 1 is a sectional view, and FIG. 2 is a plan view seen from above. In the structure of FIG. 1 and FIG. 2, the structure in which the electrodes 13 and 14 are replaced with normal electrodes is InGaAs / In.
AlAs HEMT (high electron mobility transis
tor, high electron mobility transistor), but is different from a normal HEMT in that the gate electrode is cut off in the middle, that is, a so-called split type, as shown in the figure.

It is known that in a normal HEMT, by applying a negative gate voltage of a certain magnitude to the gate electrode, a state in which the two-dimensional electron gas formed under the electrode cannot be formed can be formed. Therefore, also in this embodiment, the two-dimensional electron gas is not formed under the gate electrode, and the two-dimensional electron gas can be formed only under the cut portion of the gate electrode. FIG. 3 shows this, and FIG.
Is a cross-sectional view in a direction perpendicular to the direction. By the way, as shown in FIG. 4, when a negative voltage is applied to the gate electrode, a depletion layer shown by a dotted line in FIG. 4 is formed around the gate electrode. It becomes narrower than the split width. In this way, as shown in FIG. 5, a structure in which two two-dimensional electron gases are connected by an electron gas having a width W and a length D is formed below the gate.

The characteristic length of such a structure is as follows:
The Fermi wavelength λ _F of the two-dimensional electron gas and the mean free path l. If W is equal to or less than λ _F , an electron gas of width W and length D can be regarded as quasi-one-dimensional. If the electrode interval L in FIG. 5 is sufficiently shorter than 1,
One of the conductivity σ between the electrodes is quantized to 2e ² / h as a unit, by further gate voltage V _g, can be controlled 2e ² / h as a unit has been shown experimentally. Here, e is the electron charge, and h is Planck's constant. For the above experimental results, see BJ van Wees, H. van Houten, and CWJ B
eenakker, JG Williamson, LP Kouwenhoven, D.
"Quantized by van der Marel, and CT Foxon
Conductance of Point Contacts ina Two-Dimensional
Electron Gas ", Physical Review Lette
rs, 60, (1988), 848. The above structure is called a quantum point contact, and FIG. 6 shows an experimental result. Conductivity σ between two electrodes and resistance R
Has a relationship of σ = 1 / R, so R ₀ = h / 2e ² = 1
Assuming 2.9 kΩ, R = R ₀ / n (n = 1, 2, 3,
…)).

The InGaAs / InAlAs-based two-dimensional electron gas of this embodiment also has the above-mentioned conditions,

[0018]

(Equation 1)

If so, it has a function as a quantum point contact. Λ _F and l of the two-dimensional electron gas are given as follows.

[0020]

(Equation 2)

Here, N _s and μ are the electron concentration and the mobility of the two-dimensional electron gas, respectively. InGaAs / In
For an AlAs-based two-dimensional electron gas, μ = 60,0
The data of 00 cm ² / V _s is the best value,
GI Ng, D. Pavlidis, M. Quillec, YJ Chan, MD
"Study of the consequ by Jaffe and J. Singh
ence of excess indium in the active channel of InG
aAs / InAlAs high electron mobility transistors on d
eviceproperties ", AppliedPhysics Le
tters, 52, (1988), 728. The temperature at this time is T = 77K, N _s = 1.2 × 10 ¹² cm
^-2 . Using these values, λ _F = 23 nm, l
= 1.1 μm. Since N _s and μ hardly change below 77K, λ _F , l obtained here may be considered to be constant below 77K. Thus, in this embodiment,

[0022]

(Equation 3)

At the time, the InGaAs / InAlAs system 2
The two-dimensional electron gas also has a function as a quantum point contact.

At this time, as shown in FIG. 5, in this embodiment, a connection structure of a superconducting electrode, a two-dimensional electron gas, a quantum point contact, a two-dimensional electron gas, and a superconducting electrode is obtained. At a temperature T _C or lower, a superconducting current flows between the two superconducting electrodes via the two-dimensional electron gas and the quantum point contact. The critical current I _C at this time is obtained.

As described above, in the superconducting element, I _C and R _N
The product I _C R _N is constant. Effective element length L _eff is L
_For superconducting weakly-coupled devices satisfying _eff << l and L _eff << ξ ₀ , the "Josephson Effect in Superconductive Bridges: M" by IO Kulik and AN Omel'yanchuk
Soviet Journal o, entitled "icroscopic Theory"
f As disclosed in Low Temperature Physics, 4, (1978), 142, the following equation holds.

[0026]

(Equation 4)

Here, ξ ₀ is the coherence length of the superconductor defined by ξ ₀ = hVF / 2π ² Δ, and VF and Δ are the Fermi velocity, energy gap, φ of the superconductor, respectively.
Is the phase difference between the two superconducting electrodes, and k _B is the Boltzmann constant. In the case of the present embodiment, D can be adopted as L _eff and L << l, so that the condition of D << l is naturally satisfied. Another condition is that when VF of 2DEG is taken as VF, VF = h (2πN _s ) ^1/2 / 2πm ^* , so that the above-mentioned N _s and the effective mass m ^* at this electron concentration are obtained ^.
= 0.043me (me is the mass of the electron), and when Δ uses an energy gap of 1.5 meV of Nb, ξ
_{Since 0} = 0.1 μm, it suffices that D << 0.1 μm. However, in this embodiment, it is easy to satisfy this condition. Become. Again, this embodiment works as a quantum point contact,
The conditions to which the above equation (1) can be applied are summarized as follows.

[0028]

(Equation 5)

[0029] Therefore, now temperature of T = 0.5 K, when the superconducting electrodes and Nb, I _C R _N of the present embodiment will be 4.5mV than Equation (1). As described above, since the present embodiment also acts as a quantum point contact, R _N is, R
_N = _R0 / n (n = 1, 2, 3,..., _R0 = h / 2
e ² = 12.9 kΩ) and can be controlled by the gate voltage. Therefore, as shown in FIG. 7, I _C is 4.5 m.
V ÷ 12.9 kΩ = 0.35 μA as a unit, and is controlled by the gate voltage. As shown in FIG. 8, the current-voltage characteristics are discontinuous such as 21, 22, 23,. You can see the status. If a load straight line 27 with a load resistance R _L = 1 kΩ is drawn in this figure,
The operating point in each state is obtained as indicated by a black circle. FIG. 9 shows the relationship between the source / drain voltage and the date voltage at each operating point.
It can be seen that the drain voltage (output voltage) changes stepwise and shows a large change between the steps. The following shows that a large gain can be obtained by using this steep change.

FIG. 10 is an enlarged view of the portion circled in FIG. Assuming that had been biasing the gate voltage to the point B in FIG. If the input voltage V _in size minus the gate voltage of the point B from the gate voltage of the point A in FIG, state point C And thus in this case the output voltage V of about 1 mV
_out is obtained. Therefore, if we bias point B to reduce the V _in close to point A, the gain G = V _out / V _in will be possible to increase without limit in principle. Since in practice there are thermal noise, when too small V _in, will go to the point C by the thermal noise, the erroneous operation. The thermal noise voltage V _N to be considered is

[0031]

(Equation 6)

## EQU1 ## Here, B is a band, and the switching speed of the superconducting element of this embodiment is 100 psec (10 ps).
^-10 sec), B = 10 GHz (10 ¹⁰ Hz). Since T = 0.5K and R _L = 1kΩ, V _N =
It is 17 μV. Assuming that a signal-to-noise ratio of about 5 is sufficient, the minimum value of the input voltage is 85 μV, and the gain is as shown in Expression 7. Even if the switching speed of the superconducting element is 10 psec (10 ⁻¹¹ sec), which is 10 times faster,
A gain of about 4 can be obtained. As described above, when the load resistance R _{L is} equal to 1 kΩ, the present embodiment provides a large gain that is sufficiently practical for practical use as compared with a three-terminal element coupled with InAs or Si.

[0033]

(Equation 7)

[0034]

Embodiment 2 FIGS. 11 and 12 are views for explaining a second embodiment of the present invention. In FIG. 11, reference numeral 31 denotes a p-type InAs substrate;
Is a two-dimensional electron gas which is an n-type surface natural inversion layer, 33 and 34 are source and drain, which are superconducting electrodes, 35 is an insulating layer, 36 is a metal gate electrode, and 35 and 36 constitute an MIS type gate. Compared with the first embodiment, only the property of the two-dimensional electron gas changes, and the operation principle and the like are the same as those of the first embodiment.

In this embodiment, the two-dimensional electron gas is p
An n-type spontaneous inversion layer formed on the surface of the type InAs is used. For this, at T = 77 K, μ = 6,100 c
m ² / V _s and N _s = 8.9 × 10 ¹¹ cm ⁻² have been measured. From now on, if Nb is used as a superconducting electrode,

[0036]

(Equation 8)

Is obtained. Therefore, also in this embodiment,

[0038]

(Equation 9)

If the above condition is satisfied, an excellent superconducting three-terminal device having a large gain is provided as in the first embodiment.

[0040]

Embodiment 3 FIGS. 13 to 15 are views for explaining a third embodiment of the present invention, in which 41 is an InP substrate, 42 is non-doped InAlAs, 43 and 44 are superconducting electrodes, source and drain. , 45 are non-doped InGaAs, 4
6 is a two-dimensional electron gas formed on the 45 side of the interface between 45 and 47; 47 is non-doped InAlAs; 48 is an n-type InAlAs; 49 is an insulating layer; 50 is a metal gate electrode; And 51 is an insulated InGaAs layer. FIG. 13 is a sectional view, FIG.
4 is an enlarged view cut along AB of FIG.
In FIG. 14, reference numeral 51 denotes an insulated InGaAs layer, which is a portion insulated by implantation of, for example, Ga ions or the like, in which no two-dimensional electron gas exists. Therefore, as shown in FIG. 15, which is a view of FIG. 14 seen from above, two two-dimensional electron gases are combined with a narrow electron gas (length D, width W) as in Examples 1 and 2. With structure.

As in Example 1,

[0042]

(Equation 10)

If a certain condition is satisfied, this narrow portion works as a quantum point contact. However, in this embodiment, instead of controlling the W by the gate voltage, by controlling the electron density N _s of the two-dimensional electron gas, to obtain a function as a quantum point contact. Therefore, in the first embodiment, a negative gate voltage is applied, but in the present embodiment, a positive gate voltage needs to be applied. At this time, if the negative gate voltage in FIGS. 7 to 10 is read as positive, the same operation as in the first embodiment is performed, and a superconducting three-terminal element having a large gain and excellent is provided.

[0044]

Fourth Embodiment FIGS. 16 and 17 are views for explaining a fourth embodiment of the present invention, wherein reference numeral 61 denotes a p-type InAs substrate;
2 is a two-dimensional electron gas of the n-type surface natural inversion layer;
Is a superconducting electrode, source and drain, 65 is an insulating layer, 66
Denotes a metal gate electrode, which constitutes an MIS type gate by 65 and 66, and 71 denotes an insulated InAs layer.

FIG. 16 is a sectional view, and FIG. 17 is an enlarged sectional view of a portion of FIG. 16 from which the gate insulating film 65 and the gate electrode 66 have been removed. In comparison with Example 3, only the two-dimensional electron gas was changed to the surface inversion layer of n-type InAs.
Therefore, the width W, length D, and electrode spacing L of the narrow electron gas sandwiched between the two insulated portions 71 in FIG.

[0046]

[Equation 11]

By satisfying the above condition, the same operation as in the third embodiment is performed, and an excellent superconducting three-terminal element having a large gain is provided.

[0048]

As described above, according to the present invention, since the current-voltage characteristics of the superconducting three-terminal device can be controlled discontinuously by the gate voltage, there is an advantage that the present invention has a large gain for practical use. Therefore, in addition to the high speed and low power consumption of superconducting transistors,
High-speed digital and analog circuits for communication that operate at low temperatures,
An operation as an element constituting a high-speed logic circuit such as a computer can be expected.

[Brief description of the drawings]

FIG. 1 is a schematic sectional structural view of a semiconductor-coupled superconducting element as a first embodiment of the present invention.

FIG. 2 is a top view of FIG.

FIG. 3 is a schematic cross-sectional structure diagram in a direction perpendicular to FIG.

FIG. 4 is a diagram showing a state of a width W and a length D of an electron gas accompanying expansion of a depletion layer when a negative voltage is applied to a gate electrode.

FIG. 5 is a structural diagram in which two two-dimensional electron gases below a gate electrode are combined by an electron gas having a width W and a length D;

FIG. 6 shows the relationship between the conductivity (2e ² n / h (n = 1, 2,...)) Of a quantum point contact and the gate voltage V _g in a two-dimensional electron gas (BJ van Wees et al., Phys. Re.
v. Lett., 60, (1988), 848).

FIG. 7 shows the relationship between the current I _C of the quantum point contact and the gate voltage V _g in the first embodiment according to the present invention.

FIG. 8 shows the I _DS -V _DS characteristics of the semiconductor-coupled superconducting device according to the first embodiment of the present invention.

FIG. 9 shows the relationship between the output voltage V _DS and the gate voltage V _g of the semiconductor-coupled superconducting device according to the first embodiment of the present invention.

FIG. 10 is a partially enlarged view of FIG. 9;

FIG. 11 is a schematic sectional structural view of a semiconductor-coupled superconducting element as a second embodiment of the present invention.

FIG. 12 is a top view of FIG. 11;

FIG. 13 is a schematic sectional structural view of a semiconductor-coupled superconducting element as a third embodiment of the present invention.

FIG. 14 is an enlarged view cut along AB of FIG. 13;

FIG. 15 is a top view of FIG. 14;

FIG. 16 is a schematic sectional structural view of a semiconductor-coupled superconducting device as a fourth embodiment of the present invention.

FIG. 17 is an enlarged cross-sectional view of a portion of FIG. 16 from which a gate insulating film and a gate electrode are removed.

FIG. 18 is a schematic cross-sectional structure diagram of a conventional MIS type semiconductor coupled superconducting element using p-type InAs.

FIG. 19 is a schematic diagram of an I _DS -V _DS characteristic of the MIS semiconductor coupled superconducting element shown in FIG.

FIG. 20 is a schematic diagram of an I _DS -V _DS characteristic of a normal semiconductor FET.

[Explanation of symbols]

1,31,61 p-type InAs substrate 2,32,62 n-type natural inversion layer (two-dimensional electron gas) 3 source 4 drain 5,35,49,65 insulating layer 6 MIS type gate 7,21 gate voltage of zero -Voltage characteristics 8,22,23,24,25,26 Current-voltage characteristics when gate voltage is applied 9,27 Load straight line 11,41 InP substrate 12,42 Non-doped InAlAs 13,33,43,63 Conductive electrode (source) 14, 34, 44, 64 Superconducting electrode (drain) 15, 45 Non-doped InGaAs 16, 46 Two-dimensional electron gas 17, 47 Non-doped InAlAs 18, 48 n-type InAlAs 19 Non-doped InAlAs 20, 36 , 50, 66 Metal gate electrode 51 Insulated InGaAs layer 71 Insulated InAs layer

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-171179 (JP, A) JP-A-1-133376 (JP, A) PHYS. REV. LETT. , VOL. 60, NUMBER 9, (29 FEB RUARY 1988), PP. 848-850 SOLID STATE COMMUNICATIONS, VOL. 78, NO. 4, (APRIL 1991), PP. 299-302.

Claims (2)

(57) [Claims] 1. An interface or M at the junction of different semiconductors.
A two-dimensional electron gas formed in the surface natural inversion layer of the IS junction, two superconducting electrodes in ohmic contact with the semiconductor on which the two-dimensional electron gas is formed, and And a gate electrode for controlling a superconducting current flowing in the two-dimensional electron gas of (1), wherein the gate electrode is divided into two parts on a semiconductor.
A semiconductor-coupled superconducting device having an IS-type gate structure. 2. An interface or M at the junction of different semiconductors.
A two-dimensional electron gas formed in the surface natural inversion layer of the IS junction, two superconducting electrodes in ohmic contact with the semiconductor on which the two-dimensional electron gas is formed, and And a gate electrode for controlling a superconducting current flowing in the two-dimensional electron gas, wherein the two-dimensional electron gas has a narrow portion, and further has a MIS gate structure on the semiconductor. A semiconductor-coupled superconducting element characterized by the above-mentioned.