JPH04360589A - Semiconductor coupling superconducting element - Google Patents

Abstract

PURPOSE:To obtain a superconducting three-terminal element in which a current- voltage characteristic between a source and a drain is discontinuously controlled to a gate voltage and which has a large gain and excellent characteristics by forming a gate electrode divided into two in split type. CONSTITUTION:A semiconductor coupling superconducting element has two-dimensional electron gas 16 formed in a boundary of a junction of different semiconductors 15, 17, two superconducting electrodes 13, 14 in ohmic contact with the semiconductors formed with the gas 16, and a gate electrode 20 for controlling a superconducting current flowing in the gas 16 between the two electrodes 13 and 14. The electrode 20 is formed in a MIS type gate structure 20-19-18 split into two on the semiconductor 18. Thus, current-voltage characteristics between the source 13 and the drain 14 can be discontinuously controlled by a gate voltage to obtain a large gain for a practical use, and a superconducting transistor is excellently in high speed and low power consumption.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting element having a semiconductor at a junction, that is, a semiconductor-coupled superconducting element having a superconductor-semiconductor-superconductor bond.

0002

2. Description of the Related Art Since the invention of the tunnel-type Josephson device, much research has been conducted on superconducting three-terminal devices corresponding to bipolar transistors and field effect transistors (FETs) in semiconductors. Among these, many attempts have been made to develop semiconductor-coupled superconducting devices due to the possibility of three-terminal operation through electrical control of semiconductors, but none have been put to practical use. The main reason for this was the lack of gain or small gain of the transistor. This will be explained below using a specific example.

Typical semiconductor-coupled superconducting devices that have been realized so far include those using p-type InAs,
There is one using p-type Si.

As a semiconductor coupled superconducting device using p-type InAs, H. Takayanagi and T.
“Supercond” by Kawakami
ucting Proximity Effect i
n the Native Inversion La
Phys.
sical Review Letters 54, (
1985), 2449, or H. Takayan
agi and T. By Kawakami
”Planar-Type InAs-Coupled
Three-Terminal Supercond
ucting Devices”, D.
most ofTechnical Papers,
98, 1985 International E
lectron Device Meeting, W
ashington D. C. and a paper entitled “MIS-type InAs superconducting three-terminal device” by Takayanagi and Kawakami, Institute of Electronics and Communication Engineers Technical Research Report SCE86-23.
(1986).

In addition, as a semiconductor coupled superconducting device using p-type Si, T. Nishino, M. Miya
ke, Y. Harada and U. Kaw
“Three-Terminal” by abe
SuperconductingDeviceUsi
ng a Si Single-Crystal Fi
A paper titled ``lm'', IEEE Electr
on Devices Letters 6, (19
85), 297.

FIG. 18 shows a cross-sectional structure of a semiconductor-coupled superconducting device using p-type InAs. The source 3 and the drain 4 are made of Nb, which is a superconductor, and a superconducting current flows between the source 3 and the drain 4 via the n-type natural inversion layer 2. This superconducting current is
It is controlled by the gate voltage Vg applied to the gate 6 (lator-semiconductor).
Since it corresponds to a FET in semiconductors, it is also called a FET type superconducting transistor. FIG. 19 shows the current-voltage characteristics (source-drain current IDS vs. source-drain voltage VDS) in this element. 1 is the characteristic when the gate voltage is zero, 2 is the characteristic when the gate voltage is applied,
The point where the load line No. 3 and the two characteristics intersect, ie, A and B, are the on and off operating points of this transistor. Therefore, the voltage difference Vout between A and B becomes the output. On the other hand, since the input is Vg, the gain G of this transistor is G=Vout/Vg. Therefore, this G is specifically determined.

The current-voltage characteristic 7 in FIG. 19 consists of a superconducting state (VDS=0 state) and a normal conducting state in which resistance occurs, and the maximum value of the superconducting current flowing in the former is defined as the critical current IC, and the latter The resistance value at is called normal conduction resistance RN. In such a superconducting device, the product of IC and RN is IC
RN is approximately constant, and IC RN is approximately 1 mV when Nb is used as the superconducting electrode. This also applies to state 8 where the gate voltage is applied, and now in state 1 IC =
If 100 μA and RN = 10Ω, then in state 8, IC = 1 μA and RN = 1 kΩ, for example. That is, IC changes by about 100 μA depending on the gate voltage. The sensitivity S to Vg of IC is S=dIC/d
Defined in terms of Vg, it is measured that S=10-4 A/V in the device using the p-type InAs inversion layer shown in FIG. 18, and S=10-3 A/V in the device using Si. Therefore, it can be seen that in order to change IC by about 100 μA, a gate voltage of 1V is required for an element using InAs, and 0.1V for an element using Si. On the other hand, the output voltage Vout in this case is Vout = 100μA x RL
It can be expressed as The product of the load resistance RL representing the load line 3 in FIG. 19 and the capacitance Cg of the gate portion is a factor that determines the switching speed of this element, and RL cannot be made too large. For example, if RL = 1 kΩ, the aforementioned gain G = Vout /Vg will be 1/10 for an element using InAs and 1 for an element using Si. R.L.
By setting RN to 10 kΩ, which is 10 times as large as RN, the gains become 1 and 10, respectively, but this makes it impossible to take advantage of the high speed performance of a superconducting element. Thus, it can be seen that a large gain cannot be obtained with this type of superconducting transistor.

The reason lies in the operating principle of the FET type superconducting transistor mentioned above. This will be explained in comparison with the operation of a normal semiconductor FET. FIG. 20 shows the current-voltage characteristics (source-drain current IDS vs. source-drain voltage VDS) of a typical semiconductor FET. The current-voltage characteristics have strong nonlinearity, and the source-drain current becomes almost constant above a certain source-drain voltage. This is called the saturation region, and by using this saturation region, if we take two operating points A and B corresponding to on and off of the gate voltage as shown in the figure, the voltage between the two operating points The difference, that is, the output can be made large, and as a result, the gain also becomes large. On the other hand, as mentioned above, superconducting transistors cannot reach this saturation region because their operating current and voltage are small, about 100 μA and 0.1 V, respectively. Therefore, they cannot operate using the saturation region. Not available. For this purpose, semiconductor FET
The gain is smaller compared to

[0009]

SUMMARY OF THE INVENTION The present invention solves the problem of the conventional superconductor-semiconductor-superconductor coupling device mentioned above, namely, that the gain is too small for practical use. The aim is to realize a superconducting three-terminal device with excellent characteristics.

More specifically, one of the objects of the present invention is to provide a semiconductor coupled superconductor having an MIS type gate structure in which a gate electrode for controlling a superconducting current flowing in a two-dimensional electron gas is divided into two on a semiconductor. Another object of the present invention is to provide a conductive element.

Alternatively, one of the objects of the present invention is to provide a narrow portion in the two-dimensional electron gas in order to control the superconducting current flowing in the two-dimensional current gas, and furthermore, to provide an MIS on the semiconductor.
An object of the present invention is to provide a semiconductor-coupled superconducting device having a shaped gate structure.

0012

[Means for Solving the Problems] The present invention provides an FET-type superconducting transistor in which two-dimensional electron gas is coupled in a semiconductor, the gate structure of which is split into two, or a two-dimensional electron gas It has a narrow part inside and a normal MIS type gate on the semiconductor, and its most important feature is that the current-voltage characteristics between the source and drain can be controlled discontinuously by the gate voltage. shall be. Conventional superconducting transistors differ from each other in that they have a gate structure or a narrow portion in a two-dimensional electron gas, and in terms of operation, conventional superconducting transistors do not continuously control current-voltage characteristics. In contrast, the present invention differs in that it is controlled discontinuously.

The structure of the present invention is as shown below. That is, the present invention provides two-dimensional electron gas (16,
32), two superconducting electrodes (13, 14), (33, 34) that are in ohmic contact with the semiconductor in which the two-dimensional electron gas (6, 32) is formed, and the two superconducting electrodes (13, 14), (33, 34) In a semiconductor coupled superconducting element having a gate electrode (20, 36) that controls a superconducting current flowing in a two-dimensional electron gas (16, 32) between electrodes (13, 14), (33, 34), The gate electrode (20, 36) is a semiconductor (18
, 31) MIS type gate structure divided into two parts (2
0-19-18, 36-35-31), and has a structure as a semiconductor coupled superconducting element. Alternatively, the two-dimensional electron gas (46, 62) formed at the interface of the junction of different semiconductors (5, 7) or the surface natural inversion layer (62) of the MIS junction (66-65-61), Two superconducting electrodes (43, 44), (63, 64) are in ohmic contact with a semiconductor in which a two-dimensional electron gas (46, 62) is formed; ), 2 between (63, 64)
In a semiconductor coupled superconducting element having a gate electrode (50, 66) that controls a superconducting current flowing in the two-dimensional electron gas (46, 62), the two-dimensional electron gas (46, 62)
It has a narrow part (51, 71) inside, and a semiconductor (4
8, 61) with MIS type gate structure (50-49-48)
, 66-65-61).

[0014]

[Embodiment 1] FIGS. 1 and 2 are diagrams explaining a first embodiment of the present invention, in which 11 is an InP substrate, 12 is non-doped InAlAs, and 13 and 14 are superconducting electrodes for the source and drain. , 15 is non-doped InGaAs, 16 is a two-dimensional electron gas formed on the 15 side of the interface between 15 and 17, 17 is non-doped InAlAs, 18 is n-type In
19 is non-doped InAlAs, 20 is a metal gate electrode, and 19 and 20 constitute a MIS type gate. FIG. 1 is a sectional view, and FIG. 2 is a plan view seen from above. In the structure of FIGS. 1 and 2, the structure in which electrodes 13 and 14 are replaced with normal conduction electrodes is InGaAs/InA
lAs-based HEMT (high electron mono
It is called a high electron mobility transistor (high electron mobility transistor), but it is also called a
It differs from EMT in that, as shown in the figure, the gate electrode is cut in the middle, which is what is called a split shape.

[0015] In a normal HEMT, it is known that by applying a certain level of negative gate voltage to the gate electrode, a state can be made in which the two-dimensional electron gas formed under the electrode cannot be formed. Therefore, in this embodiment as well, two-dimensional electron gas is not formed under the gate electrode, and it is possible to form two-dimensional electron gas only under the cut portion of the gate electrode. This is shown in Figure 3, and Figure 1
is a cross-sectional view taken in a right angle direction. By the way, as shown in FIG. 4, when a negative voltage is applied to the gate electrode, a depletion layer is formed around it as indicated by the dotted line in the figure, and as a result, the width W of the electron gas is equal to the cut width of the gate electrode, i.e. Narrower than the split width. In this way, as shown in FIG. 5, a structure in which two two-dimensional electron gases are coupled by an electron gas having a width W and a length D is formed under the gate.

[0016] The characteristic length of such a structure is
Fermi wavelength λF and mean free path l of two-dimensional electron gas
However, if W is the same as or less than λF, the electron gas of width W and length D can be regarded as quasi-one-dimensional, and furthermore, if the electrode spacing L in Fig. 5 is sufficiently shorter than l, then Ba, 2
The conductivity σ between the two electrodes is quantized in units of 2e2/h, and is further reduced to 2e2/h by the gate voltage Vg.
It has been experimentally shown that it can be controlled as a unit. Here, e is the electron charge and h is Planck's constant. Regarding the above experimental results, please refer to B. J. van Wees, H.
van Houten, C. W. J. Beena
ker, J. G. Williamson, L. P
．． Kouwenhoven, D. van der
Marel, and C. T. “Quantized Conductance” by Foxon
of Point Contacts in Two
-Dimensional Electron Gas
”, a paper titled, Physical Review
Letters, 60, (1988), 848
As disclosed in . The above structure is called a quantum point contact, and the experimental results are shown in FIG. Since the conductivity σ between two electrodes and the resistance R are in the relationship σ=1/R, if R0 = h/2e2=12.9kΩ, then R=R0/n(n=1,2,3,・It can also be said to be quantization of resistance in the form of...).

The InGaAs/InAlAs two-dimensional electron gas of this example also meets the above conditions, namely

[0018]

[Math 1]

If it is, it has a function as a quantum point contact. λF and l of the two-dimensional electron gas are given as follows.

[0020]

[Math 2]

[0021] Here, Ns and μ are the electron concentration and mobility of the two-dimensional electron gas, respectively. InGaAs/I
For nAlAs-based two-dimensional electron gas, μ=60,
000cm2/Vs is the best value, and G. I. Ng, D. Pavlidis, M.
．． Quillec, Y. J. Chan, M. D.
Jaffe and J. “S” by Singh
study of the consequence o
f excel indium in the ac
tive channel of InGaAs/In
AlAs high electron mobile
ty transistors on device
Appli
edPhysics Letters, 52, (1
988), 728. The temperature at this time is T = 77K, Ns = 1.2 x 1012c
It is m-2. Using these values, λF = 23n
m, l=1.1 μm. Since Ns and μ hardly change below 77K, λF and l obtained here are:
It can be considered that it is constant at 77K or less. In this way, also in this example,

[0022]

[Math 3]

When 2 of the InGaAs/InAlAs system
Dimensional electron gas will also function as a quantum point contact.

At this time, as shown in FIG. 5, in this example, the connection structure is superconducting electrode-two-dimensional electron gas-quantum point contact-two-dimensional electron gas-superconducting electrode, and the criticality of the superconducting electrode is At a temperature below TC, a superconducting current flows between both superconducting electrodes via a two-dimensional electron gas and a quantum point contact. Find the critical current IC at this time.

As mentioned above, in a superconducting device, IC and R
The product of N IC RN is constant. Effective element length Le
In a superconducting weakly coupled device where ff satisfies Leff <<l and Leff <<ξ0, I. O. Kulik
and A. N. ``Josephson Effect in S'' by Omel'yanchuk
superconductive Bridges: M
icroscopic Theory”, Soviet Journal of Low T
empire physics, 4, (1
978), 142, the following equation holds.

[0026]

[Math 4]

Here, ξ0 is ξ0 = hVF/2π2
The coherence length of the superconductor defined by Δ, VF, Δ is the Fermi velocity of the superconductor and the energy gap, φ is the phase difference between two superconducting electrodes, and kB is the Boltzmann constant. In this example, D as Leff
can be adopted and L<<l, so naturally the condition D<<l is satisfied. Another condition is 2DE as VF
Taking the VF of G, VF=h(2πNs)1/2/
2πm*, the above-mentioned Ns, the effective mass m* at this electron concentration = 0.043me (me is the mass of the electron), and the energy gap of Nb as Δ.
If 5 meV is used, ξ0 = 0.1 μm, so
It is sufficient if D<<0.1 μm, but it is easy to satisfy this condition in this example, and at this time, the previous equation (1
) can be used. Once again, the conditions under which this embodiment works as a quantum point contact and the above formula (1) is applicable are summarized as follows.

[0028]

[Math 5]

Therefore, assuming that the temperature is T=0.5K and the superconducting electrode is Nb, IC RN in this example is 4.5 mV from the above equation (1). As mentioned above, since this example also works as a quantum point contact, RN is
RN = R0 /n (n = 1, 2, 3, ..., R0
= h/2e2 = 12.9 kΩ), and can be controlled by the gate voltage. Therefore, as shown in FIG.
is controlled by the gate voltage in units of 4.5 mV ÷ 12.9 kΩ = 0.35 μA, and as shown in Figure 8, the current-voltage characteristics are 21, 22, 2
It can be seen that the state takes a discontinuous state such as 3,... If a load straight line 27 with a load resistance RL = 1 kΩ is drawn in this diagram, the operating points in each state can be found as black circles. Figure 9 shows the relationship between the source-drain voltage and the date voltage at each operating point. The source-drain voltage (output voltage) changes stepwise with respect to the gate voltage (input voltage). It can be seen that there are large changes between steps. It will be shown below that a large gain can be obtained by utilizing this steep change.

FIG. 10 is an enlarged view of the circled portion in FIG. Now, if the gate voltage is biased to point B in the figure, if there is an input voltage Vin equal to the gate voltage at point A minus the gate voltage at point B, the state is C.
point, resulting in an output voltage V of about 1 mV in this case
out is obtained. Therefore, if the bias point B is brought closer to the point A and Vin is decreased, the gain G=Vout
/Vin can be made as large as desired in principle. In reality, thermal noise exists, so if Vin is made too small, this thermal noise will cause the sensor to move to point C, resulting in malfunction. The thermal noise voltage VN to be considered is:

[0031]

[Math 6]

[0032] Here, B is the band, and the switching speed of the superconducting element in this example is 100 psec (10-
10 sec), then B = 10 GHz (1010 Hz
). Since T=0.5K and RL=1kΩ,
It is found that VN = 17μV. Assuming that a signal-to-noise ratio of about 5 is sufficient, the minimum value of the input voltage will be 85 μV, and the gain will be as shown in Equation 7. The switching speed of superconducting elements is 10 times faster than 10 psec (10-11 sec).
), a gain of about 4 can be obtained. In this way, when the same load resistance RL = 1kΩ, InAs and Si
This embodiment provides a large gain that is sufficient for practical use, compared to a three-terminal element coupled with a three-terminal element.

[0033]

[Math 7]

[0034]

[Embodiment 2] FIGS. 11 and 12 are diagrams explaining a second embodiment of the present invention, in which 31 is a p-type InAs substrate, 32
is an n-type surface natural inversion layer for two-dimensional electron gas, 33 and 34 are superconducting electrodes for source and drain, 35 is an insulating layer, 36 is a metal gate electrode, and 35 and 36 constitute a MIS type gate. Compared to Example 1, the only difference is the properties of the two-dimensional electron gas, and the operating principle is the same as Example 1.

In this example, p is used as the two-dimensional electron gas.
An n-type natural inversion layer formed on the InAs surface is used, for which T=77K and μ=6,100cm.
2 /Vs, Ns = 8.9 x 1011 cm-2 has been actually measured. From now on, if Nb is used as a superconducting electrode,

[0036]

[Math. 8]

##EQU1## Therefore, also in this example

[
0038

[Math. 9]

If the following is satisfied, an excellent superconducting three-terminal element with a large gain can be provided as in the first embodiment.

[0040]

[Embodiment 3] FIGS. 13 to 15 are diagrams explaining a third embodiment of the present invention, in which 41 is an InP substrate, 42 is non-doped InAlAs, and 43 and 44 are superconducting electrodes for the source and drain. , 45 is non-doped InGaAs, 4
6 is a two-dimensional electron gas formed on the 45 side of the interface between 45 and 47, 47 is undoped InAlAs, 48 is n-type InAlAs, 49 is an insulating layer, 50 is a metal gate electrode, and 49 and 50 form an MIS type gate. 51 is an insulated InGaAs layer. Figure 13 is a cross-sectional view, Figure 1
4 is an enlarged view taken along line AB in FIG. 13. Reference numeral 51 in FIG. 14 is an insulated InGaAs layer, which is a portion insulated by, for example, implantation of Ga ions, etc., and no two-dimensional electron gas exists in this portion. Therefore, as shown in FIG. 15, which is a top view of FIG. Has a structure.

Similar to Example 1,

[0042]

[Math. 10]

If the following conditions are satisfied, this narrow portion acts as a quantum point contact. However, in this example, W is not controlled by the gate voltage, but by controlling the electron concentration Ns of the two-dimensional electron gas,
Obtains functionality as a quantum point contact. Therefore,
In Example 1, a negative gate voltage was applied, but in this example, it is necessary to apply a positive gate voltage. At this time, if the negative gate voltages in FIGS. 7 to 10 are replaced with positive values, the device operates in the same way as in Example 1, providing an excellent superconducting three-terminal device with a large gain.

[0044]

[Embodiment 4] FIGS. 16 and 17 are diagrams explaining a fourth embodiment of the present invention, in which 61 is a p-type InAs substrate;
2 is an n-type surface natural inversion layer, which is a two-dimensional electron gas, 63, 64
are superconducting electrodes, source and drain, 65 is an insulating layer, 66
are metal gate electrodes 65 and 66 forming an MIS type gate, and 71 is an insulated InAs layer.

FIG. 16 is a cross-sectional view, and FIG. 17 is an enlarged cross-sectional view of a portion of FIG. 16 from which the gate insulating film 65 and gate electrode 66 are removed. Compared to Example 3, the two-dimensional electron gas was simply changed to a surface natural inversion layer of n-type InAs. Therefore, the width W, length D, and electrode spacing L of the narrow electron gas sandwiched between the two insulated parts 71 in FIG. 17 are the same as in Example 2.

[0046]

[Math. 11]

By satisfying the following, the device operates in the same manner as in Example 3, providing an excellent superconducting three-terminal device with a large gain.

[0048]

As explained above, the present invention has the advantage of having a large gain that can be put to practical use because the current-voltage characteristics of a superconducting three-terminal element can be controlled discontinuously by the gate voltage. Therefore, in addition to the high speed and low power consumption of superconducting transistors, taking advantage of their high gain,
High-speed digital and analog circuits for communications that operate at low temperatures,
It can be expected to operate as an element constituting high-speed logic circuits such as computers.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional structural diagram of a semiconductor coupled superconducting device as a first embodiment of the present invention.

FIG. 2 is a top view of FIG. 1;

FIG. 3 is a schematic cross-sectional structure diagram taken in a direction perpendicular to FIG. 1;

FIG. 4 is a diagram showing the width W and length D of electron gas as the depletion layer expands when a negative voltage is applied to the gate electrode.

FIG. 5 is a structural diagram in which two two-dimensional electron gases below the gate electrode are coupled by an electron gas having a width W and a length D.

[Fig. 6] Relationship between conductivity of quantum point contact (2e2 n/h (n = 1, 2...)) and gate voltage Vg in two-dimensional electron gas (B.J. van Wees
References by Phys. Rev. Lett. , 60
, (1988), 848).

FIG. 7 shows the relationship between the current IC of the quantum point contact and the gate voltage Vg in the first embodiment according to the present invention.

FIG. 8 shows IDS-VDS characteristics of a semiconductor coupled superconducting device as a first example according to the present invention.

FIG. 9 shows the relationship between the output voltage VDS and gate voltage Vg of a semiconductor coupled superconducting device as a first embodiment of the present invention.

FIG. 10 is a partially enlarged view of FIG. 9;

FIG. 11 is a schematic cross-sectional structural diagram of a semiconductor coupled superconducting device as a second embodiment of the present invention.

FIG. 12 is a top view of FIG. 11;

FIG. 13 is a schematic cross-sectional structural diagram of a semiconductor coupled superconducting device as a third embodiment of the present invention.

FIG. 14 is an enlarged view taken along line AB in FIG. 13;

FIG. 15 is a top view of FIG. 14;

FIG. 16 is a schematic cross-sectional structural diagram of a semiconductor coupled superconducting device as a fourth embodiment of the present invention.

17 is an enlarged cross-sectional view of a portion of FIG. 16 from which the gate insulating film and gate electrode are removed.

FIG. 18 is a schematic cross-sectional structural diagram of a conventional MIS type semiconductor coupled superconducting element using p-type InAs.

19 is a schematic diagram of IDS-VDS characteristics of the MIS type semiconductor coupled superconducting element shown in FIG. 18. FIG.

FIG. 20 is a schematic diagram of IDS-VDS characteristics of a normal semiconductor FET.

[Explanation of symbols]

1, 31, 61 p-type InAs substrate 2, 32, 62 n-type natural inversion layer (two-dimensional electron gas)
3 Source 4 Drain 5, 35, 49, 65 Insulating layer 6 MIS gate 7, 21 Current-voltage characteristics when gate voltage is zero 8,
22, 23, 24, 25, 26 Current-voltage characteristics when applying gate voltage 9, 27 Load line 11, 41 InP substrate 12, 42 Non-doped InAlAs 13, 33,
43, 63 Superconducting electrode (source) 14, 34, 44
, 64 Superconducting electrode (drain) 15, 45 Non-doped InGaAs 16, 46 Two-dimensional electron gas 17, 47 Non-doped InAlAs 18, 48
n-type InAlAs 19 Non-doped InAlAs 20, 36, 50, 66 Metal gate electrode 51 Insulated InGaAs layer 71 Insulated InAs layer

Claims (2)

[Claims] Claim 1: A two-dimensional electron gas formed at the interface of junctions of different semiconductors or a surface natural inversion layer of an MIS junction, and two-dimensional electron gas in ohmic contact with the semiconductor on which the two-dimensional electron gas is formed. In a semiconductor-coupled superconducting device having two superconducting electrodes and a gate electrode that controls a superconducting current flowing in a two-dimensional electron gas between the two superconducting electrodes, the gate electrode is divided into two parts on the semiconductor. A semiconductor-coupled superconducting device characterized by having a MIS type gate structure. [Claim 2] A two-dimensional electron gas formed at the interface of junctions of different semiconductors or a surface natural inversion layer of an MIS junction, and two-dimensional electron gas that is in ohmic contact with the semiconductor on which the two-dimensional electron gas is formed. In a semiconductor coupled superconducting device having two superconducting electrodes and a gate electrode for controlling a superconducting current flowing in a two-dimensional electron gas between the two superconducting electrodes, a narrow portion is formed in the two-dimensional electron gas. What is claimed is: 1. A semiconductor-coupled superconducting device comprising: a semiconductor-coupled superconducting device;