JPH09298294A - Heterojunction field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the contact resistance, by making the source and drain electrodes of an ordinary conductive metal and forming a direct Ohmic contact of a channel layer to the source and drain electrodes. SOLUTION: Source and drain electrode-forming parts are etched down to an InAlAs layer 10, a source and drain electrode metals 1, 2 are contacted with the side face of an InAs layer 6 such that this layer 6 is inserted into an InGaAs channel layer of the conventional reverse structure HEMT as deep as several nanometers and two-dimensional electron channel layer is formed in this layer 6. The electrons incident to the two-dimensional channel layer from the source electrode metal is free from scattering until arriving at below the gate electrode, and hence they harristically run to below the electrode with keeping a high energy. Thus, it is possible to improve electron velocity and mutual conductance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high electron mobility transistor having an InAlAs gate contact layer / InGaAs channel layer / InAlAs carrier supply layer / InAlAs buffer layer.

[0002]

2. Description of the Related Art A cross-sectional structure of a high electron mobility transistor having an InAlAs gate contact layer / InGaAs channel layer / InAlAs carrier supply layer / InAlAs buffer layer is shown in FIG. 7 (a). 12 is an alloy ohmic electrode (source), 13 is an alloy ohmic electrode (drain), 14
Is a metal gate electrode, 15 is a region alloyed with an alloy, 4 is a non-doped InAlAs layer, and 16 is a non-doped
InGaAs layer, 8 undoped InAlAs layer, 9 n-type I
nAlAs layer, 10 is undoped InAlAs layer, 11 is InP
It is a substrate. Thus, a high electron mobility transistor (HEMT) having a carrier supply layer below a channel layer is
It is usually called a reverse structure HEMT. A band diagram when a gate voltage is applied to this structure to form a two-dimensional electron channel layer is shown in FIG. 7 (b). In the figure, E _{0 to} E ₄ represent quantum levels in the channel layer. It is known that this structure exhibits better device characteristics than the forward structure HEMT having a carrier supply layer on the channel layer because the two-dimensional electron channel layer approaches the gate.

It is necessary to make ohmic contact between the two-dimensional electron channel layer and the metal to be the source and drain electrodes so that the contact resistance is as low as possible. Normal,
As the ohmic contact method, the alloy ohmic method shown in FIG. 7 or the non-alloy ohmic method shown in FIG. 8 is used. The alloy ohmic method is used as an electrode, for example.
After forming AuGe, the sample is heated to a high temperature to sinter the alloy layer of AuGe and the semiconductor to the channel layer and make ohmic contact with the two-dimensional electron channel layer.

On the other hand, the non-alloy ohmic method reduces the thickness of the depletion layer extending to the InAlAs gate contact layer by inserting an n-type InGaAs layer / n-type InAlAs layer between the source and drain electrode metals and the InAlAs gate contact layer. However, ohmic contact is made possible by the mirror effect and increase in tunnel current. However, in either method, since an alloy layer or a depletion layer exists between the source and drain electrode metals and the secondary electron channel layer, the high energy of the electrons transferred from the electrode metal to the secondary electron channel layer is present. Was relaxed by the scattering process in these layers.

In the case of the inverse structure HEMT, since the non-doped InAlAs gate contact layer exists between the source / drain electrode and the two-dimensional electron channel layer, the source / drain electrode contacts the two-dimensional electron channel layer. For this purpose, AuGe-based alloy ohmic electrodes were indispensable. In this case, there are problems that (i) it is difficult to reduce the contact resistance in a fine pattern, (ii) the uniformity and reproducibility are poor, and (iii) the change with time due to heat is large.

On the other hand, the noise figure F of this system is expressed by the following equation.

[0007]

[Equation 1]

Where K _f is a fitting factor,
ω is a frequency, C _GS is a source-gate capacitance, g _m is a transconductance, R _G is a gate resistance, and R _S is a source resistance. As can be seen from this equation, since the noise figure F is greatly affected by the magnitudes of the gate resistance R _G and the source resistance R _S , it is necessary to reduce these resistance values. The source resistance can be reduced by reducing the contact resistance and increasing the mobility. On the other hand, the gate resistance is
The gate electrode is miniaturized to improve the switching speed, but this increases the resistance value. As described above, it has been difficult in the past to improve the switching speed and reduce the noise figure at the same time.

[0009]

[Problems to be Solved by the Invention] As described above, In
AlAs Gate contact layer / InGaAs channel layer / InAlAs
In a conventional high electron mobility transistor having a carrier supply layer / InAlAs buffer layer, it is necessary to lower the contact resistance at each electrode in order to reduce the noise figure, but on the other hand, in order to ensure high speed operation. A fine pattern is required, which makes it difficult to reduce the contact resistance. These are in a mutually contradictory relationship, and have been a problem in improving the performance of this type of transistor. Therefore, the present invention aims to secure ohmic contact in each electrode portion of the high electron mobility transistor and to reduce the contact resistance.

[0010]

In order to achieve the above object, in the present invention, the source electrode and the drain electrode are made of a normal conductive metal, and the two-dimensional electron layer is directly ohmic-contacted with the contact. The structure reduces the resistance.

According to the second aspect of the present invention, the source electrode and the drain electrode are made of a superconductor, and the ohmic contact with the two-dimensional electronic layer directly reduces the contact resistance, thereby reducing the source resistance. There is.

In the third aspect, the gate electrode is made of a superconductor, and the channel layer is in direct ohmic contact with the source electrode and the drain electrode without a barrier layer.

According to a fourth aspect of the present invention, each of the gate, source and drain electrodes is made of a superconductor, and the channel layer is in direct ohmic contact with the source and drain electrodes.

In claim 5, the carrier supply layer is I
It is stated that the present invention is also applicable when the nAlAs and channel layers are made of different materials such as InGaAs and these two layers are formed separately.

Furthermore, in the present invention, the transconductance of the channel layer is improved by inserting an InAs layer inside the channel layer.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

[0017]

First Embodiment FIG. 1 shows an example of a device structure according to an embodiment of the present invention. 1 is a source electrode metal, 2 is a drain electrode metal, 3 is a gate electrode metal, 4 is undoped
InAlAs layer, 5 is a non-doped InGaAs layer, 6 is a non-doped InAs layer, 7 is a non-doped InGaAs layer, 8 is a non-doped InAlAs layer, 9 is an n-type InAlAs layer, 10 is a non-doped InAlAs layer, 11 is an InP substrate. is there. This structure uses InA for the source and drain electrode portions 1 and 2.
The lAs layer 10 is also removed by wet etching or dry etching, and the source and drain electrode metals 1 and 2 are brought into contact with the side surfaces of the InAs layer 6 to form the layer. The InAs layer 6 is inserted to a thickness of 2 to 6 nm in the InGaAs channel layer 16 of the conventional inverted structure HEMT shown in FIG. In the structure shown in FIG. 1, the two-dimensional electron channel layer is formed in the InAs layer 6 and the InAs layer 6 is formed.
Is 4 nm, the carrier concentration at 300 K is n _s =
2.3 × 10 ¹² cm- ² , mobility μ = 15000 cm ² / Vs, 7
N _s = 2.3 × 10 ¹² cm ~ ^{2 at} 7K, μ = 84900 c
m ^{2 /} Vs, n _{s at} 4.2K = 2.3 × 10 ¹² cm ~ ² ,
μ = 110800 cm ² / Vs was obtained.

FIG. 2 is a diagram schematically showing the potential distribution near the interface between the source electrode metal and the two-dimensional electron channel layer of this structure. The Schottky barrier height of the InAs layer has been confirmed to be almost zero, but there is a potential barrier due to the difference in carrier concentration at the source electrode metal / InAs interface. Therefore, the source
The voltage applied between the drain electrodes will be applied to this interface. At this time, the electrons that have passed through the potential barrier from the source electrode metal to the two-dimensional electron channel layer through the tunnel process acquire high energy corresponding to the voltage applied to the interface. On the other hand, the mean free path of the electron gas in the two-dimensional electron channel layer is 0.37 μm at 300 K and 2.1 μ at 77 K due to the above high electron transport characteristics.
At 4.2K, it becomes 2.8 μm. The mean free path of 77K or less is the normal source-gate electrode spacing (0.5 to 1).
It is sufficiently longer than μm), so there is no scattering during this period.
That is, the electrons that have entered the two-dimensional electron channel layer from the source electrode metal do not undergo scattering until they reach under the gate electrode, so that they travel ballistically under the gate electrode and can maintain high energy.

On the other hand, the mutual conductance g _{m, which} is a standard for estimating the device performance, is an amount proportional to the average electron velocity of electrons passing under the gate electrode. The electrons that have entered the two-dimensional electron channel layer from the source electrode metal pass under the gate electrode with a high energy, that is, a high electron velocity as the initial velocity, so the average electron velocity increases. as a result,
The mutual conductance g _m can be increased as compared with the case where the source and drain electrodes are brought into contact with the two-dimensional electron electron channel layer by the conventional alloy ohmic method or non-alloy ohmic method. FIG. 3 shows a comparison between the present structure at 4.2 K, which depends on the gate length of the transconductance g _m , and the conventional HEMT having the reverse structure of alloy ohmic. From this figure, it was found that the ohmic contact of the source and drain electrode metals with the two-dimensional electron channel layer directly increased the transconductance g _m more than double.

In the above embodiment, the inverted structure HEM is used.
Although T is used, the same effect can be expected by using a forward structure HEMT. In addition, conventional In
Similar effects can be expected in GaAs HEMTs and other field effect transistors.

[0021]

Second Embodiment FIG. 4A shows an element structure according to another embodiment of the present invention. In the figure, the source electrode 1
9, the drain electrode 20 and the gate electrode 21 are all electrodes using a superconductor, and are non-doped InAlAs layer 4, non-doped InGaAs layer 5, non-doped InAs layer 6, non-doped InGaAs layer 7, non-doped InAlAs layer, n type
InAlAs layer 9 and non-doped InAlAs layer 10 are each In
It is formed on the P substrate 11. Note that in the following, Nb is used as the superconductor of each of the above electrodes, but NbN
It is also possible to use such compound superconductors and oxide superconductors represented by YBa ₂ Cu ₃ O ₇ .

The InAs layer 6 is 2 to 6 nm in the InGaAs channel layer 16 of the conventional reverse structure HEMT shown in FIG.
Is inserted with the thickness of. In the structure shown in FIG. 4, the two-dimensional electron channel layer is formed in this InAs layer, and it is confirmed that the mobility is increased. (For example, T. Akazaki, K. Arai,
T.Enoki, Y. Ishii, IEEE electron Dev. Lett., Vol.1
3, p. 325, 1992) A band diagram when a gate voltage is applied to this structure to form a two-dimensional electron channel layer is shown in FIG. This figure shows a quantum well formed by an InAs layer in the channel layer. InAs
Since the Schottky barrier height of the layer is negative, it is possible to reduce the contact resistance as compared with the case where the source and drain electrodes are in contact with the two-dimensional electron channel layer by alloy ohmic. In FIG. 5, the reverse structure HE of the structure according to the present invention and the conventional alloy ohmic HE at 4.2K.
A comparison of the contact resistance R _C with MT is shown. From this figure, it was found that the contact resistance was reduced to about 1/4 as expected. In addition, the structure HE according to the present invention at 4.2K shown in FIG.
The mutual conductances g _m obtained from the current-voltage characteristics with MT were 650 mS / mm and 440 mS / mm, respectively. From this, it was found that the reduction of the contact resistance can increase the transconductance g _m by about 50%. In addition, in the present invention, since the source, drain and gate electrodes are formed of a superconductor, the resistance at each electrode portion can be ignored up to a high frequency of THz level. This means that the source resistance and the gate resistance are reduced, and it is shown that the noise figure shown in the equation (1) can be dramatically reduced.

In the above embodiment, the inverted structure HEM is used.
Although T is used, the same effect can be expected by using a forward structure HEMT.

[0024]

As described above, according to the present invention,
By making ohmic contact of the source and drain electrode metals directly with the two-dimensional electron channel layer, an increase in electron velocity can be obtained, and as a result, an increase in transconductance can be realized.

Also, to reduce the contact resistance,
Also, by using a gate electrode formed of a superconductor, it is possible to reduce the gate resistance, and as a result, it is possible to increase the transconductance and reduce the noise figure.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an InGaAs inverted structure HEMT in which an InAs layer is inserted into an InGaAs channel layer in which source and drain electrodes are directly in ohmic contact with a two-dimensional electron channel layer.

2A is a schematic diagram of a potential distribution in the vicinity of an interface between a source electrode metal and a two-dimensional electron channel layer before (a) a drain voltage is applied and (b) after a drain voltage is applied. FIG.

FIG. 3 is a characteristic diagram showing a comparison (4.2K) between the present embodiment of the gate length dependence of transconductance and the conventional HEMT having an inverted structure of alloy ohmic.

4A is a sectional view of an InGaAs reverse structure HEMT having a superconducting electrode and an InAs layer inserted in an InGaAs channel layer, and FIG. 4B is a band diagram of the structure according to the present invention.

FIG. 5: HE of the present invention and a conventional alloy ohmic structure HE
FIG. 4 is a voltage-current characteristic diagram at 4.2K for comparing contact resistance with MT.

[Fig. 6] 4.2K of HEMT with inverted structure of alloy ohmic
6A and 6B are voltage-current characteristic diagrams in FIG. 3A, which is a characteristic diagram of the present invention, and FIG.

7A is a cross-sectional view of a conventional InGaAs inverse structure HEMT, and FIG. 7B is a band diagram of this conventional structure.

FIG. 8: Conventional HEM using non-alloy ohmic method
Sectional drawing of T.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Source electrode 2 ... Drain electrode 3 ... Gate electrode 4 ... Non-doped InAlAs layer 5 ... Non-doped InGaAs layer 6 ... Non-doped InAs layer 7 ... Non-doped InGaAs 8 ... Non-doped InAlAs layer 9 ... N-type InAlAs layer 10 ... Non-doped InAlAs layer 11 ... InP substrate 12 ... Alloy ohmic electrode (source) 13 ... Alloy ohmic electrode (drain) 14 ... Metal gate electrode 15 ... Region alloyed with alloy 16 ... Non-doped InGaAs layer 17 ... n-type InGaAs layer 18 ... n-type InAlAs layer 19 ... superconducting electrode (source) 20 ... superconducting electrode (drain) 21 ... superconducting electrode (gate)

Claims (6)

[Claims] 1. In a heterojunction field effect transistor in which the carrier concentration of a channel layer is modulated by a gate electrode, the source and drain electrodes are made of normal conductive metal, and the channel layer is directly ohmic with the source and drain electrodes. A heterojunction field effect transistor, characterized in that it is in contact with. 2. In a heterojunction field effect transistor in which the carrier concentration of a channel layer is modulated by a gate electrode, the source and drain electrodes are made of a superconductor,
A heterojunction field effect transistor, wherein the channel layer is in direct ohmic contact with the source and drain electrodes. 3. A heterojunction field effect transistor in which the carrier concentration of a channel layer is modulated by a gate electrode, wherein the gate electrode is made of a superconductor. 4. A heterojunction field effect transistor in which the carrier concentration of a channel layer is modulated by a gate electrode, wherein the gate, source and drain electrodes are made of a superconductor, and the channel layer comprises the source and drain electrodes. A heterojunction field effect transistor, which is in direct ohmic contact. 5. The heterojunction field effect transistor according to claim 1, wherein the carrier supply layer and the channel layer are separated, the carrier supply layer is made of InAlAs, and the channel layer is made of InGaAs. A heterojunction field effect transistor characterized by being provided. 6. The heterojunction field effect transistor according to claim 5, wherein an InAs layer is inserted inside the channel layer.