JPS631758B2 - - Google Patents
Info
- Publication number
- JPS631758B2 JPS631758B2 JP10414080A JP10414080A JPS631758B2 JP S631758 B2 JPS631758 B2 JP S631758B2 JP 10414080 A JP10414080 A JP 10414080A JP 10414080 A JP10414080 A JP 10414080A JP S631758 B2 JPS631758 B2 JP S631758B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- gate
- semiconductor substrate
- drain
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 14
- 230000005641 tunneling Effects 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 6
- 239000002344 surface layer Substances 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 4
- 239000010408 film Substances 0.000 description 14
- 239000010410 layer Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0895—Tunnel injectors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
本発明はトンネル効果を利用した新規な構造の
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device with a novel structure that utilizes the tunnel effect.
半導体物性工学の進歩に基づいて多種類の半導
体素子が考案され、使用されているが、その内に
サイリスタと呼ばれている制御整流素子があるこ
とは周知の通りであり、該サイリスタにも各種の
構造が知られている。第１図はその代表的なゲー
ト電極を設けた三端子サイリスタの構造模型図
で、PNPNダイオードのP2部分にゲート電極１
を形成し、ゲート電極から流れ込むゲート電流に
よつて、陽極２と陰極３間を阻止状態（OFF）
から導通状態（ON）に変えるスイツチ素子で、
ゲート電流の大きさを変えてブレークオーバ電圧
（VBO）を制御することができるものである。 Many types of semiconductor devices have been devised and used based on advances in semiconductor physics engineering, and it is well known that one of these devices is a controlled rectifying device called a thyristor. The structure of is known. Figure 1 is a structural model of a three-terminal thyristor with a typical gate electrode.
is formed, and the gate current flowing from the gate electrode blocks the connection between the anode 2 and the cathode 3 (OFF).
A switch element that changes from to conductive state (ON).
The breakover voltage (V BO ) can be controlled by changing the magnitude of the gate current.
この様なサイリスタと同様の原理により動作す
るスイツチ素子として、絶縁膜のトンネル効果を
応用したMIST（Metal Insulator Silicon
Thyrister）が提案されており、これは薄膜の形
成が容易となつた結果と考えられる。（参考文
献：Solid State Electronics Vol 22 PP 589）
第２図にその構造を示しているが、例えばP+型
半導体基板４上にＮ型エピタキシヤル層５を成長
させ、20〜50Åの薄い酸化シリコン（SiO2）膜
６上に陰極３を設け、半導体基板４の裏面をオー
ミツクに接続して陽極２とし、エピタキシヤル層
５内にN+型不純物領域であるゲート領域である
ゲート領域７を形成して、これにオーミツクなゲ
ート電極１を接続した構造であり、その動作は陽
極２と陰極３間に電圧を加えても、SiO2膜６で
導通が阻止されてOFF状態であるが、ゲートに
電圧を与えてゲート電流を流し、N+型ゲート領
域７より多量の電子をＮ型エピタキシヤル層５に
注入すると、該Ｎ型層５は過剰電子量となつて、
トンネリングが起こり、OFF状態からON状態に
切り換わる。 MIST (Metal Insulator Silicon
Thyrister) has been proposed, and this is thought to be a result of the ease of forming thin films. (Reference: Solid State Electronics Vol 22 PP 589)
The structure is shown in FIG. 2. For example, an N-type epitaxial layer 5 is grown on a P + type semiconductor substrate 4, and a cathode 3 is provided on a thin silicon oxide (SiO 2 ) film 6 of 20 to 50 Å. , the back surface of the semiconductor substrate 4 is ohmicly connected to serve as the anode 2, a gate region 7 which is an N + type impurity region is formed in the epitaxial layer 5, and an ohmic gate electrode 1 is connected to this. Even if a voltage is applied between the anode 2 and the cathode 3, conduction is blocked by the SiO 2 film 6, resulting in an OFF state. When a larger amount of electrons than the type gate region 7 is injected into the N-type epitaxial layer 5, the N-type layer 5 has an excess amount of electrons.
Tunneling occurs and the state switches from OFF to ON.
ところで、このMISTと称するスイツチ素子は
トンネル現象を用いているので伝導の温度依存性
が少ない長所があるが、導通に寄与するのはP+
型半導体基板より注入された少数キヤリアのホー
ルであるから、スイツチの切換え速度が今一度遅
いことが難点である。本発明はかような欠点を除
去して高速動作を可能とした半導体素子を提案す
るもので、同じ伝導型の低濃度表層を形成したＮ
型（又はＰ型）半導体基板上にトンネリングの可
能な半絶縁薄膜を介してソース電極を設け、基板
をドレインとし、且つ低濃度表層にＰ型（又はＮ
型）不純物からなるゲートを設け、該ゲートに加
える電圧によつてソース・ドレイン間のトンネル
電流を制御することを特徴とするトンネルFET
（電界効果トランジスタ）である。 By the way, this switch element called MIST uses tunneling phenomenon, so it has the advantage of less temperature dependence of conduction, but it is P + that contributes to conduction.
Since the hole is a minority carrier injected from the type semiconductor substrate, the switching speed of the switch is once again slow. The present invention proposes a semiconductor device that eliminates such drawbacks and enables high-speed operation.
A source electrode is provided on a semi-insulating thin film capable of tunneling on a semiconductor substrate (or P type), the substrate is used as a drain, and a P type (or N
A tunnel FET characterized in that a gate made of impurity (type) is provided and the tunnel current between the source and drain is controlled by the voltage applied to the gate.
(field effect transistor).
以下、本発明を一実施例により詳細に説明する
と、第３図はその構造断面図を示し、１１はゲー
ト電極、１２はドレイン電極、１３はソース電
極、１４はN+型半導体基板、１５はＮ型表層、
１６はソース電極直下のトンネリングの可能な
SiO2膜からなる半絶縁膜、１７はP+型不純物領
域である。その形成方法はN+型半導体基板１４
にＮ型エピタキシヤル層１５を成長し、その面上
に膜厚数10ÅのSiO2膜１６を700℃程度の低温度
酸化により形成させる。P+型不純物領域はレジ
スト膜をマスクとして、イオン注入法により形成
するが、ソース電極を取り囲んだリング形状に形
成する。又、トンネリングを行なわせる半絶縁膜
はSiO2膜の代りに窒化シリコン（Si3N4）膜や多
結晶シリコン膜を使用してもよい。第３図を第２
図と比較すれば判る様に、その構造は上記に説明
したMIST形サイリスタと類型の構造で、同じく
薄膜のトンネリングを利用したものであるが、そ
の動作原理は縦型接合FETやSIT（Static
Induction Transistor）と同様である。即ちゲー
ト電圧を印加しない場合に、ソース・ドレイン間
に一定値以上の電圧を加えるとN+型半導体基板
１４からＮ型表層１５に過剰の電子が入り込み、
半絶縁膜１６近傍のポテンシヤルを下げてトンネ
リングが起つて電流が流れ、ON状態となる。ゲ
ート電圧が印加されると、Ｎ型表層１５内にゲー
ト電圧に応じた空乏層が発生し、ゲート電圧が大
きくなる空乏層も厚くなつて、N+型半導体基板
１４からの電子の流れ込みも少なくなり、ある値
以上のゲート電圧となれば半絶縁膜１６近傍のポ
テンシヤルが上つてトンネリングが阻止され、ソ
ース・ドレイン間はOFF状態となる。第４図は
この様なOFF状態のポテンシヤル図、第５図は
ON状態のポテンシヤル図を示すものである。こ
の様に動作して本発明の半導体素子はスイツチン
グ用に用いることができるが、多数キヤリヤが伝
導に寄与するために、スイツチングの応答速度は
早くて、且つ上記のMIST形サイリスタと同じく
トンネル効果を用いるので、動作の温度依存性は
小さい。又、電極はアルミニウム層などを用いて
オーミツク接続をはかるが、ゲート電極は絶縁膜
上にあり、微妙な電極コンタクト不良の問題も解
消される。 Hereinafter, the present invention will be explained in detail with reference to an embodiment. FIG. 3 shows a cross-sectional view of its structure, in which 11 is a gate electrode, 12 is a drain electrode, 13 is a source electrode, 14 is an N + type semiconductor substrate, and 15 is a N-type surface layer,
16 is capable of tunneling directly under the source electrode.
A semi-insulating film made of SiO 2 film, 17 is a P + type impurity region. The formation method is N + type semiconductor substrate 14
An N-type epitaxial layer 15 is grown on the surface of the N-type epitaxial layer 15, and a SiO 2 film 16 with a thickness of several tens of angstroms is formed on the surface by low-temperature oxidation at about 700°C. The P + type impurity region is formed by ion implantation using a resist film as a mask, and is formed in a ring shape surrounding the source electrode. Further, as the semi-insulating film for tunneling, a silicon nitride (Si 3 N 4 ) film or a polycrystalline silicon film may be used instead of the SiO 2 film. Figure 3 is 2
As can be seen by comparing it with the figure, its structure is similar to the MIST type thyristor explained above, and it also uses thin film tunneling, but its operating principle is similar to that of vertical junction FETs and SIT (static
Induction Transistor). That is, when no gate voltage is applied, if a voltage of a certain value or more is applied between the source and drain, excessive electrons enter the N type surface layer 15 from the N + type semiconductor substrate 14.
By lowering the potential near the semi-insulating film 16, tunneling occurs and current flows, resulting in an ON state. When a gate voltage is applied, a depletion layer corresponding to the gate voltage is generated in the N-type surface layer 15, and as the gate voltage increases, the depletion layer also becomes thicker, and the flow of electrons from the N + type semiconductor substrate 14 also decreases. Therefore, when the gate voltage exceeds a certain value, the potential near the semi-insulating film 16 increases, blocking tunneling and turning off the source-drain region. Figure 4 is a potential diagram for such an OFF state, and Figure 5 is a potential diagram for such an OFF state.
This shows a potential diagram in the ON state. Operating in this manner, the semiconductor device of the present invention can be used for switching, but since the majority carrier contributes to conduction, the response speed of switching is fast and, like the above-mentioned MIST type thyristor, it has no tunnel effect. Since the temperature dependence of the operation is small. Further, although the electrodes are made of an aluminum layer or the like for ohmic connection, the gate electrode is on the insulating film, which eliminates the problem of subtle electrode contact failures.
以上、説明した様に本発明は高速動作を初め利
点の多い半導体素子であり、FETの発展に大き
く功献するもので、その応用範囲は広い。尚、上
記はN+型半導体基板を用いた実施例で説明した
が、すべて反対導電型によつても同じく本発明の
トンネルFETを形成することもできる。 As described above, the present invention is a semiconductor device that has many advantages including high speed operation, and has greatly contributed to the development of FETs, and has a wide range of applications. Although the above example uses an N + -type semiconductor substrate, the tunnel FET of the present invention can also be formed using opposite conductivity types.
第１図はサイリスタの構造模型、第２図は公知
のMIST形サイリスタ構造図、第３図は本発明の
トンネルFET構造図で、第４図・第５図はその
ポテンシヤル図である。
図中、１１はゲート電極、１２はドレイン電
極、１３はソース電極、１４はN+型半導体基板、
１５はＮ型低濃度表層、１６はトンネリングの可
能な半絶縁膜、１７はP+型不純物領域（ゲート
領域）を示している。
FIG. 1 is a structural model of a thyristor, FIG. 2 is a structural diagram of a known MIST type thyristor, FIG. 3 is a structural diagram of a tunnel FET of the present invention, and FIGS. 4 and 5 are potential diagrams thereof. In the figure, 11 is a gate electrode, 12 is a drain electrode, 13 is a source electrode, 14 is an N + type semiconductor substrate,
Reference numeral 15 indicates an N-type low concentration surface layer, 16 a semi-insulating film capable of tunneling, and 17 a P + -type impurity region (gate region).
Claims (1)
体基板上にトンネリングの可能な半絶縁薄膜を介
してソース電極を設け、基板をドレインとし、且
つ低濃度表層にＰ型（又はＮ型）不純物領域から
なるゲートを設け、該ゲートに加える電圧によつ
てソース・ドレイン間のトンネル電流を制御する
ことを特徴とするトンネルFET。1. A source electrode is provided on an N-type (or P-type) semiconductor substrate with a low-concentration surface layer formed thereon via a semi-insulating thin film that allows tunneling, and the substrate is used as a drain, and a P-type (or N-type) semiconductor substrate is formed on the low-concentration surface layer. A tunnel FET characterized in that a gate made of an impurity region is provided, and a tunnel current between a source and a drain is controlled by a voltage applied to the gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10414080A JPS5730368A (en) | 1980-07-29 | 1980-07-29 | Tunnel fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10414080A JPS5730368A (en) | 1980-07-29 | 1980-07-29 | Tunnel fet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5730368A JPS5730368A (en) | 1982-02-18 |
| JPS631758B2 true JPS631758B2 (en) | 1988-01-13 |
Family
ID=14372785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10414080A Granted JPS5730368A (en) | 1980-07-29 | 1980-07-29 | Tunnel fet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5730368A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0624264B2 (en) * | 1986-02-04 | 1994-03-30 | 工業技術院長 | Field effect transistor |
| JP3431706B2 (en) * | 1994-12-16 | 2003-07-28 | 新日本石油化学株式会社 | Laminate, nonwoven fabric or woven fabric and reinforced laminate using them |
| US6054086A (en) * | 1995-03-24 | 2000-04-25 | Nippon Petrochemicals Co., Ltd. | Process of making high-strength yarns |
| DE69629560T2 (en) * | 1996-02-23 | 2004-06-17 | Nippon Petrochemicals Co., Ltd. | WEB LAMINATION DEVICE |
-
1980
- 1980-07-29 JP JP10414080A patent/JPS5730368A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5730368A (en) | 1982-02-18 |
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