JPH02192220A - オン状態からオフ状態へ、およびオフ状態からオン状態へスイツチングできる出力バツフア回路 - Google Patents
オン状態からオフ状態へ、およびオフ状態からオン状態へスイツチングできる出力バツフア回路Info
- Publication number
- JPH02192220A JPH02192220A JP1240926A JP24092689A JPH02192220A JP H02192220 A JPH02192220 A JP H02192220A JP 1240926 A JP1240926 A JP 1240926A JP 24092689 A JP24092689 A JP 24092689A JP H02192220 A JPH02192220 A JP H02192220A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- circuit
- state
- output
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000630 rising effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 241000270708 Testudinidae Species 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09425—Multistate logic
- H03K19/09429—Multistate logic one of the states being the high impedance or floating state
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Dram (AREA)
- Electronic Switches (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US246.634 | 1988-09-19 | ||
| US07/246,634 US4877978A (en) | 1988-09-19 | 1988-09-19 | Output buffer tri-state noise reduction circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02192220A true JPH02192220A (ja) | 1990-07-30 |
Family
ID=22931521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1240926A Pending JPH02192220A (ja) | 1988-09-19 | 1989-09-19 | オン状態からオフ状態へ、およびオフ状態からオン状態へスイツチングできる出力バツフア回路 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4877978A (enExample) |
| JP (1) | JPH02192220A (enExample) |
Families Citing this family (52)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0821846B2 (ja) * | 1989-02-03 | 1996-03-04 | 日本電気株式会社 | ワイアード信号ドライブ回路 |
| US5013940A (en) * | 1989-11-03 | 1991-05-07 | Cypress Semiconductor Corporation | Multi stage slew control for an IC output circuit |
| JP3024774B2 (ja) * | 1990-03-16 | 2000-03-21 | 沖電気工業株式会社 | 回路素子 |
| US5140192A (en) * | 1990-08-01 | 1992-08-18 | Motorola, Inc. | Bicmos logic circuit with self-boosting immunity and a method therefor |
| US5179299A (en) * | 1990-11-05 | 1993-01-12 | Ncr Corporation | Cmos low output voltage bus driver |
| US5162672A (en) * | 1990-12-24 | 1992-11-10 | Motorola, Inc. | Data processor having an output terminal with selectable output impedances |
| JP3225528B2 (ja) * | 1991-03-26 | 2001-11-05 | 日本電気株式会社 | レジスタ回路 |
| US5146111A (en) * | 1991-04-10 | 1992-09-08 | International Business Machines Corporation | Glitch-proof powered-down on chip receiver with non-overlapping outputs |
| US5194760A (en) * | 1991-12-23 | 1993-03-16 | Motorola, Inc. | Slew rate limited inductive load driver |
| US5245230A (en) * | 1992-03-06 | 1993-09-14 | Ohri Kul B | Low substrate injection n-channel output stage |
| US5214320A (en) * | 1992-06-12 | 1993-05-25 | Smos Systems, Inc. | System and method for reducing ground bounce in integrated circuit output buffers |
| US5341046A (en) * | 1992-12-07 | 1994-08-23 | Ncr Corporation | Threshold controlled input circuit for an integrated circuit |
| KR950000353B1 (ko) * | 1992-12-30 | 1995-01-13 | 현대전자산업 주식회사 | 집적회로용 출력 버퍼 회로 |
| JP3029958B2 (ja) * | 1993-01-18 | 2000-04-10 | シャープ株式会社 | 半導体記憶装置 |
| EP0620649B1 (en) * | 1993-03-18 | 1997-09-10 | NCR International, Inc. | Transceiver circuit for an integrated circuit |
| JP2896305B2 (ja) * | 1993-05-15 | 1999-05-31 | 株式会社東芝 | 半導体集積回路装置 |
| US5467455A (en) * | 1993-11-03 | 1995-11-14 | Motorola, Inc. | Data processing system and method for performing dynamic bus termination |
| US6118261A (en) * | 1993-11-08 | 2000-09-12 | International Business Machines Corp. | Slew rate control circuit |
| JPH07212211A (ja) * | 1994-01-13 | 1995-08-11 | Fujitsu Ltd | 出力バッファ回路 |
| US5440258A (en) * | 1994-02-08 | 1995-08-08 | International Business Machines Corporation | Off-chip driver with voltage regulated predrive |
| US5677642A (en) * | 1994-11-01 | 1997-10-14 | At&T Global Information Solutions Company | Signal generator with supply voltage tolerance |
| US5701090A (en) * | 1994-11-15 | 1997-12-23 | Mitsubishi Denki Kabushiki Kaisha | Data output circuit with reduced output noise |
| US5568084A (en) * | 1994-12-16 | 1996-10-22 | Sgs-Thomson Microelectronics, Inc. | Circuit for providing a compensated bias voltage |
| US5793247A (en) * | 1994-12-16 | 1998-08-11 | Sgs-Thomson Microelectronics, Inc. | Constant current source with reduced sensitivity to supply voltage and process variation |
| FR2730367A1 (fr) * | 1995-02-08 | 1996-08-09 | Bull Sa | Coupleur d'entree sortie de circuit integre |
| US5528166A (en) * | 1995-03-14 | 1996-06-18 | Intel Corporation | Pulse controlled impedance compensated output buffer |
| JPH098612A (ja) * | 1995-06-16 | 1997-01-10 | Nec Corp | ラッチ回路 |
| US5835970A (en) * | 1995-12-21 | 1998-11-10 | Cypress Semiconductor Corp. | Burst address generator having two modes of operation employing a linear/nonlinear counter using decoded addresses |
| US5903174A (en) * | 1995-12-20 | 1999-05-11 | Cypress Semiconductor Corp. | Method and apparatus for reducing skew among input signals within an integrated circuit |
| US6043684A (en) * | 1995-12-20 | 2000-03-28 | Cypress Semiconductor Corp. | Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit |
| US6411140B1 (en) | 1995-12-20 | 2002-06-25 | Cypress Semiconductor Corporation | Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit |
| US5787291A (en) * | 1996-02-05 | 1998-07-28 | Motorola, Inc. | Low power data processing system for interfacing with an external device and method therefor |
| US5834859A (en) * | 1996-11-18 | 1998-11-10 | Waferscale Integration, Inc. | Battery backed configurable output buffer |
| US5732027A (en) * | 1996-12-30 | 1998-03-24 | Cypress Semiconductor Corporation | Memory having selectable output strength |
| US6133751A (en) * | 1998-08-05 | 2000-10-17 | Xilinx, Inc. | Programmable delay element |
| US5841296A (en) * | 1997-01-21 | 1998-11-24 | Xilinx, Inc. | Programmable delay element |
| US5959481A (en) * | 1997-02-18 | 1999-09-28 | Rambus Inc. | Bus driver circuit including a slew rate indicator circuit having a one shot circuit |
| US5889416A (en) * | 1997-10-27 | 1999-03-30 | Cypress Semiconductor Corporation | Symmetrical nand gates |
| US6097222A (en) * | 1997-10-27 | 2000-08-01 | Cypress Semiconductor Corp. | Symmetrical NOR gates |
| US6278295B1 (en) | 1998-02-10 | 2001-08-21 | Cypress Semiconductor Corp. | Buffer with stable trip point |
| US6023176A (en) * | 1998-03-27 | 2000-02-08 | Cypress Semiconductor Corp. | Input buffer |
| US6496033B2 (en) | 1998-06-08 | 2002-12-17 | Cypress Semiconductor Corp. | Universal logic chip |
| US6542004B1 (en) | 2000-06-20 | 2003-04-01 | Cypress Semiconductor Corp. | Output buffer method and apparatus with on resistance and skew control |
| JP3573701B2 (ja) * | 2000-09-14 | 2004-10-06 | Necエレクトロニクス株式会社 | 出力バッファ回路 |
| JP4022040B2 (ja) * | 2000-10-05 | 2007-12-12 | 松下電器産業株式会社 | 半導体デバイス |
| EP1237279A1 (en) * | 2001-02-21 | 2002-09-04 | STMicroelectronics S.r.l. | Output buffer with automatic control of the switching speed as a function of the supply voltage and temperature |
| US7202699B1 (en) | 2003-09-15 | 2007-04-10 | Cypress Semiconductor Corporation | Voltage tolerant input buffer |
| US7394293B1 (en) | 2003-09-25 | 2008-07-01 | Cypress Semiconductor Corp. | Circuit and method for rapid power up of a differential output driver |
| US7888962B1 (en) | 2004-07-07 | 2011-02-15 | Cypress Semiconductor Corporation | Impedance matching circuit |
| US8036846B1 (en) | 2005-10-20 | 2011-10-11 | Cypress Semiconductor Corporation | Variable impedance sense architecture and method |
| US7876133B1 (en) | 2006-09-27 | 2011-01-25 | Cypress Semiconductor Corporation | Output buffer circuit |
| US10476502B2 (en) * | 2017-04-28 | 2019-11-12 | Cirrus Logic, Inc. | Control of switches in a variable impedance element |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3737673A (en) * | 1970-04-27 | 1973-06-05 | Tokyo Shibaura Electric Co | Logic circuit using complementary type insulated gate field effect transistors |
| US3973139A (en) * | 1973-05-23 | 1976-08-03 | Rca Corporation | Low power counting circuits |
| US4217502A (en) * | 1977-09-10 | 1980-08-12 | Tokyo Shibaura Denki Kabushiki Kaisha | Converter producing three output states |
| US4329600A (en) * | 1979-10-15 | 1982-05-11 | Rca Corporation | Overload protection circuit for output driver |
| US4585958A (en) * | 1983-12-30 | 1986-04-29 | At&T Bell Laboratories | IC chip with noise suppression circuit |
| JPS60177723A (ja) * | 1984-02-24 | 1985-09-11 | Hitachi Ltd | 出力回路 |
| US4723108A (en) * | 1986-07-16 | 1988-02-02 | Cypress Semiconductor Corporation | Reference circuit |
-
1988
- 1988-09-19 US US07/246,634 patent/US4877978A/en not_active Expired - Lifetime
-
1989
- 1989-09-19 JP JP1240926A patent/JPH02192220A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US4877978A (en) | 1989-10-31 |
| US4877978B1 (enExample) | 1992-10-27 |
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